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1. 发明授权

US06830998B1 Gate dielectric quality for replacement metal gate transistors 失效
标题翻译：更换金属栅极晶体管的栅极介电质量得到改善
公开(公告)号：US06830998B1
公开(公告)日：2004-12-14
申请号：US10462667
申请日：2003-06-17
申请人： James Pan , Paul Besser , Christy Mei-Chu Woo , Minh Van Ngo , Jinsong Yin
发明人： James Pan , Paul Besser , Christy Mei-Chu Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L213205
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.
摘要翻译：在更换金属栅极处理期间由于等离子体损坏引起的栅极介质劣化被固化并且通过在去除多晶硅栅极之后处理栅极电介质来防止进一步的等离子体劣化。实施例包括在金属沉积之前的金属沉积和CMP之后的低温真空退火，在氧气和氩气中的退火，在金属沉积之前的臭氧或形成气体，或者在金属沉积之前的硅烷或乙硅烷中的热浸渍。

2. 发明授权

US06861350B1 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
标题翻译：一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极
公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译：微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中的富硅钽硅氮化物。在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

3. 发明授权

US06893910B1 One step deposition method for high-k dielectric and metal gate electrode 有权
标题翻译：一种用于高k电介质和金属栅电极的沉积方法
公开(公告)号：US06893910B1
公开(公告)日：2005-05-17
申请号：US10462670
申请日：2003-06-17
申请人： Christy Mei-Chu Woo , Paul R. Besser , Minh Van Ngo , James N. Pan , Jinsong Yin
发明人： Christy Mei-Chu Woo , Paul R. Besser , Minh Van Ngo , James N. Pan , Jinsong Yin
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/78 , H01L21/338 , H01L21/31 , H01L21/3205
CPC分类号： H01L21/28185 , H01L21/28079 , H01L21/28194 , H01L21/31683 , H01L29/4958 , H01L29/511 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/7833
摘要： A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a Ta2O5 region and a Ta region from the deposited oxide and Ta. This creates a low carbon-content Ta2O5 and a metallic Ta gate in a single process step.
摘要翻译：用于形成半导体结构的方法去除形成在电介质层上的临时栅极以暴露其中沉积有富氧CVD氧化物的凹槽。然后通过低功率物理气相沉积在CVD氧化物上沉积钽层。然后进行退火以从沉积的氧化物和Ta形成Ta 2 O 5区域和Ta区域。这在单一工艺步骤中产生低碳含量的Ta 2 O 5 O 5和金属Ta浇口。

4. 发明授权

US06548403B1 Silicon oxide liner for reduced nickel silicide bridging 有权
标题翻译：用于还原硅化镍桥接的氧化硅衬垫
公开(公告)号：US06548403B1
公开(公告)日：2003-04-15
申请号：US09679871
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo
发明人： Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L29/6659
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by forming a relatively thick silicon oxide liner on the side surfaces of the gate electrode and adjacent surface of the semiconductor substrate before forming the silicon nitride sidewall spacers thereon. Embodiments include forming a silicon dioxide liner at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers thereon.
摘要翻译：在形成氮化硅侧壁之前，通过在栅电极的侧表面和半导体衬底的相邻表面上形成相对较厚的氧化硅衬垫来防止在栅电极上的硅化镍层与氮化硅侧壁间隔物之间的源极/漏极区之间的桥接垫片。在形成氮化硅侧壁间隔物之前，实施例包括在大约至大约600埃的厚度形成二氧化硅衬垫。

5. 发明授权

US06432817B1 Tungsten silicide barrier for nickel silicidation of a gate electrode 有权
标题翻译：用于栅电极的硅化硅的硅化钨屏障
公开(公告)号：US06432817B1
公开(公告)日：2002-08-13
申请号：US09731024
申请日：2000-12-07
申请人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George Kluth
发明人： Jacques J. Bertrand , Christy Mei-Chu Woo , Minh Van Ngo , George Kluth
IPC分类号： H01L214763
CPC分类号： H01L29/4941 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of tungsten silicide thereon and an upper polycrystalline silicon layer on the tungsten silicide layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and the tungsten silicide barrier layer prevents nickel from reacting with the lower polycrystalline silicon layer.
摘要翻译：使用硅化钨阻挡层来控制栅电极的镍硅化。实施例包括在硅化钨层上形成包括下多晶硅层，硅化钨层和上多晶硅层的栅电极结构，沉积镍层和硅化层，由此将上多晶硅层转变为镍硅化物和硅化钨阻挡层防止镍与下部多晶硅层反应。

6. 发明授权

US06661067B1 Nitrogen-plasma treatment for reduced nickel silicide bridging 有权
标题翻译：氮等离子体处理用于还原硅化镍桥接
公开(公告)号：US06661067B1
公开(公告)日：2003-12-09
申请号：US10260514
申请日：2002-10-01
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser , Robert A. Huertas
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Paul R. Besser , Robert A. Huertas
IPC分类号： H01L2994
CPC分类号： H01L29/665 , H01L21/3115 , Y10S257/90
摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译：通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

7. 发明授权

US06657304B1 Conformal barrier liner in an integrated circuit interconnect 有权
标题翻译：集成电路互连中的保形阻挡衬垫
公开(公告)号：US06657304B1
公开(公告)日：2003-12-02
申请号：US10165510
申请日：2002-06-06
申请人： Christy Mei-Chu Woo , Minh Van Ngo , John E. Sanchez, Jr. , Steven C. Avanzino
发明人： Christy Mei-Chu Woo , Minh Van Ngo , John E. Sanchez, Jr. , Steven C. Avanzino
IPC分类号： H01L2352
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76871 , H01L21/76876 , H01L2221/1089
摘要： A manufacturing method, and an integrated circuit resulting therefrom, has a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.
摘要翻译：一种制造方法和由此产生的集成电路在其上具有基板和半导体器件。衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

8. 发明授权

US06593237B1 Method for manufacturing a low dielectric constant stop layer for integrated circuit interconnects 失效
标题翻译：制造用于集成电路互连的低介电常数阻挡层的方法
公开(公告)号：US06593237B1
公开(公告)日：2003-07-15
申请号：US10179047
申请日：2002-06-24
申请人： Minh Van Ngo , Christy Mei-Chu Woo
发明人： Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L23/5329 , H01L21/76807 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口和填充沟道开口的导体芯。在通道电介质层上形成通孔停止层，使氢浓度低于15原子％，并且在通孔停止层上方形成通孔电介质层，并具有通孔。通孔电介质层上的第二通道介电层具有第二通道开口。填充第二通道开口和通孔开口的第二导体芯连接到半导体器件。

9. 发明授权

US06525428B1 Graded low-k middle-etch stop layer for dual-inlaid patterning 有权
标题翻译：用于双镶嵌图案的分级低k中间蚀刻停止层
公开(公告)号：US06525428B1
公开(公告)日：2003-02-25
申请号：US10183458
申请日：2002-06-28
申请人： Minh Van Ngo , Steven C. Avanzino , Christy Mei-Chu Woo , John E. Sanchez
发明人： Minh Van Ngo , Steven C. Avanzino , Christy Mei-Chu Woo , John E. Sanchez
IPC分类号： H01L2348
CPC分类号： H01L21/76832 , H01L21/76807 , H01L23/5222 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , Y10S438/931 , H01L2924/00
摘要： Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.
摘要翻译：改进的蚀刻选择性，阻挡金属润湿和降低的互连电容通过实施使用包括第一碳化硅层，第一碳化硅上的富硅层和第二碳化硅层上的第二碳化硅层的分级中间蚀刻停止层的镶嵌加工来实现富硅层。实施例包括在下部封装的Cu线上顺序沉积多孔低k电介质层，沉积渐变的中间蚀刻停止层，在分级中间蚀刻停止层上沉积多孔低k电介质层，形成双镶嵌开口露出在沟槽开口的底部的富硅表面，沉积种子层，沉积阻挡中间层，如Ta或Ta / TaN复合材料，并用Cu填充开口。

10. 发明授权

US06507123B1 Nickel silicide process using UDOX to prevent silicide shorting 有权
标题翻译：使用UDOX的硅化镍工艺防止硅化物短路
公开(公告)号：US06507123B1
公开(公告)日：2003-01-14
申请号：US09679878
申请日：2000-10-05
申请人： Christy Mei-Chu Woo , Minh Van Ngo , Jacques J. Bertrand
发明人： Christy Mei-Chu Woo , Minh Van Ngo , Jacques J. Bertrand
IPC分类号： H01L27088
CPC分类号： H01L29/665 , H01L29/6656
摘要： A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide. first and second sets of sidewall spacers and nickel suicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first set of sidewall spacers are formed undoped silicon oxide and are respectively disposed adjacent the first and second sidewalls. The second set of sidewall spacers are formed from silicon nitride and are respectively disposed adjacent the first set of sidewall spacers. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. The second set of sidewall spacers being formed from undoped silicon oxide prevents the formation of nickel silicide on the second set of sidewall spacers. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译： MOSFET半导体器件包括衬底，栅电极，栅极氧化物。第一和第二组侧壁间隔物和镍硅化物层。栅极氧化物设置在栅极电极和衬底之间，并且衬底包括源极/漏极区域。栅电极具有第一和第二相对的侧壁，并且第一组侧壁间隔物形成为未掺杂的氧化硅，并且分别设置在第一和第二侧壁附近。第二组侧壁间隔件由氮化硅形成，并且分别设置在第一组侧壁间隔件附近。硅化镍层设置在源/漏区和栅电极上。由未掺杂的氧化硅形成的第二组侧壁间隔件防止在第二组侧壁间隔物上形成硅化镍。还公开了制造半导体器件的方法。

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