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1. 发明授权

US11039674B2 Breakage resistant light bulb headband 有权
公开(公告)号：US11039674B2
公开(公告)日：2021-06-22
申请号：US16748984
申请日：2020-01-22
申请人： Connie Wang
发明人： Connie Wang
IPC分类号： A45D8/36 , F21V23/02 , F21V17/16 , F21V23/00 , F21W121/06 , F21V23/04
摘要： A breakage resistant light bulb headband having increased flexibility includes a single piece injection-molded main body with integral bulb holding structures, a clip-on battery case, and wiring that connects light sources and a power source in the battery case by extending along an outside surface of the headband so as to eliminate the need for an internal passage, and a relatively thick multiple piece construction.

2. 外观设计

USD698958S1 Luminous stick 有权
公开(公告)号：USD698958S1
公开(公告)日：2014-02-04
申请号：US29439866
申请日：2012-12-17
申请人： Connie Wang , Wei Hung Yu
设计人： Connie Wang , Wei Hung Yu

3. 发明申请

US20120176779A1 LUMINOUS PRODUCT STRUCTURE 审中-公开
标题翻译： LUMINOUS产品结构
公开(公告)号：US20120176779A1
公开(公告)日：2012-07-12
申请号：US13004910
申请日：2011-01-12
申请人： Connie WANG , Wei Hung Yu
发明人： Connie WANG , Wei Hung Yu
IPC分类号： F21L4/02
CPC分类号： G09F13/22
摘要： This invention is a luminous product structure, in particular one that takes advantage of the special design of a product's dazzling body to create a dazzling effect, making the product more attractive; it includes a casing and a luminous unit; the casing has a dazzling casing which has a series of multiangular diamond-cut dazzling bodies joined to surrounding raised strips; the luminous unit comprises of a circuit board and a luminous unit and can be fitted into inside of the casing, the aforementioned design allowing the luminous unit to glitter and, in conjunction with the multi-face light refraction special feature, effectively increasing the novelty and added-value of the product.
摘要翻译：本发明是一种发光产品结构，特别是利用产品令人眼花缭乱的身体特殊设计的产品结构，使产品更具吸引力; 它包括一个外壳和一个发光单元; 外壳具有令人眼花缭乱的外壳，其具有连接到周围的凸起条的一系列多角形钻石切割的耀眼体; 发光单元包括电路板和发光单元，并且可以装配到壳体的内部，上述设计允许发光单元闪烁，并且与多面光折射特殊功能相结合，有效地增加了新颖性，产品附加值。

4. 发明申请

US20110095370A1 WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：集成电路存储器件中的电阻降低方法和结构
公开(公告)号：US20110095370A1
公开(公告)日：2011-04-28
申请号：US12961379
申请日：2010-12-06
申请人： Shenqing FANG , Jihwan CHOI , Connie WANG , Eunha KIM
发明人： Shenqing FANG , Jihwan CHOI , Connie WANG , Eunha KIM
IPC分类号： H01L29/78
CPC分类号： H01L27/11573 , G11C5/063 , H01L21/823468 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/665 , H01L29/66507
摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
摘要翻译：公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对多晶硅从字线低电阻。

5. 发明授权

US07867899B2 Wordline resistance reduction method and structure in an integrated circuit memory device 有权
标题翻译：集成电路存储器件中的字线电阻降低方法和结构
公开(公告)号：US07867899B2
公开(公告)日：2011-01-11
申请号：US12111886
申请日：2008-04-29
申请人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
发明人： Shenqing Fang , Jihwan Choi , Connie Wang , Eunha Kim
IPC分类号： H01L21/44 , H01L21/02
CPC分类号： H01L27/11573 , G11C5/063 , H01L21/823468 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/665 , H01L29/66507
摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
摘要翻译：公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对多晶硅从字线低电阻。

6. 发明授权

US07838429B2 Method to manufacture a thin film resistor 有权
标题翻译：制造薄膜电阻的方法
公开(公告)号：US07838429B2
公开(公告)日：2010-11-23
申请号：US11779465
申请日：2007-07-18
申请人： Tony Phan , Kyle M. Flessner , Martin B. Mollat , Connie Wang , Arthur Pan , Eric William Beach , Michelle R. Keramidas , Karen Elizabeth Burks
发明人： Tony Phan , Kyle M. Flessner , Martin B. Mollat , Connie Wang , Arthur Pan , Eric William Beach , Michelle R. Keramidas , Karen Elizabeth Burks
IPC分类号： H01L21/302
CPC分类号： H01L28/20 , H01L21/8221 , H01L27/0688
摘要： A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.
摘要翻译：一种用于制造半导体器件的方法，该方法包括通过包括在半导体衬底上沉积电阻材料层的工艺来形成薄膜电阻器。该方法还包括在电阻材料层上沉积绝缘层，以及在绝缘层上进行第一干蚀刻工艺以形成绝缘体。该方法还包括在电阻材料层上执行第二干蚀刻工艺以形成电阻体。电阻体和绝缘体具有基本相同的周长。

7. 发明申请

US20100078815A1 Ruthenium interconnect with high aspect ratio and method of fabrication thereof 有权
标题翻译：具有高纵横比的钌互连及其制造方法
公开(公告)号：US20100078815A1
公开(公告)日：2010-04-01
申请号：US12286149
申请日：2008-09-29
申请人： Zheng Wang , Connie Wang , Erik Wilson , Wen Yu , Robert Chiu
发明人： Zheng Wang , Connie Wang , Erik Wilson , Wen Yu , Robert Chiu
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L23/485 , H01L21/76877 , H01L23/53252 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.
摘要翻译：导电互连通过介电层中的开口设置，电连接两个导电层。在一个实施例中，互连由完全填充介电层中的开口的钌形成。在另一个实施方案中，在提供钌之前，在开口中提供钛的粘附层。在使用这种方法时，可实现20:1或更大的纵横比（互连长度与其宽度之比）。

8. 发明申请

US20090268500A1 WORDLINE RESISTANCE REDUCTION METHOD AND STRUCTURE IN AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：集成电路存储器件中的电阻降低方法和结构
公开(公告)号：US20090268500A1
公开(公告)日：2009-10-29
申请号：US12111886
申请日：2008-04-29
申请人： Shenqing FANG , Jihwan CHOI , Connie WANG , Eunha KIM
发明人： Shenqing FANG , Jihwan CHOI , Connie WANG , Eunha KIM
IPC分类号： G11C5/06 , H01L21/8234
CPC分类号： H01L27/11573 , G11C5/063 , H01L21/823468 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/665 , H01L29/66507
摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.
摘要翻译：公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对多晶硅从字线低电阻。

9. 发明授权

US06939803B2 Method for forming conductor reservoir volume for integrated circuit interconnects 有权
标题翻译：用于形成集成电路互连的导体储存器容积的方法
公开(公告)号：US06939803B2
公开(公告)日：2005-09-06
申请号：US10225656
申请日：2002-08-21
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76838 , H01L21/76873 , H01L21/76874 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层。器件介电层上的第一介电层具有形成在其中的开口，其中包括导体储存器体积。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。除了第一通道开口之外，阻挡层沿着第二通道和通孔开口。导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。导体储存器容积提供导体材料供应，以防止在第一通道和通孔中形成空隙。

10. 发明授权

US06841473B1 Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap 有权
标题翻译：制造具有低溶解度金属导体互连帽的集成电路
公开(公告)号：US06841473B1
公开(公告)日：2005-01-11
申请号：US10672126
申请日：2003-09-26
申请人： Pin-Chin Connie Wang , Steven C. Avanzino
发明人： Pin-Chin Connie Wang , Steven C. Avanzino
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76849 , H01L21/76855 , H01L21/76858 , H01L21/76862 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.
摘要翻译：提供了一种具有半导体器件的半导体衬底的集成电路的制造方法。形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有形成在其中的开口。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。铈导体互连帽设置在导电芯上方，在电介质层和铈导体互连帽上方具有覆盖层。

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