专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07058919B1 Methods of generating test designs for testing specific routing resources in programmable logic devices 失效
标题翻译：生成用于测试可编程逻辑器件中特定路由资源的测试设计的方法
公开(公告)号：US07058919B1
公开(公告)日：2006-06-06
申请号：US10696357
申请日：2003-10-28
申请人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
发明人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
IPC分类号： G06F17/50
CPC分类号： G01R31/318516 , G01R31/31704
摘要： Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.
摘要翻译：直接针对PLD中的指定路由资源的方法，例如路由需要测试的资源。使用目标路由资源实现可观察网络的测试设计。 PLD路由器用于从目标路由资源向后路由PLD的路由结构到可观察网络的源。网络基于源标识，网络的负载被标识为路由器负载目标。路由器然后用于从目标路由资源转发到网络上的一个负载。可以针对目标路由资源列表重复此过程，以提供尽可能多的目标路由资源的测试设计。可以创建其他测试设计来测试剩余的目标路由资源。在其他实施例中，路由器首先向前路由，然后向后路由。

2. 发明授权

US07143384B1 Methods of routing programmable logic devices to minimize programming time 失效
标题翻译：路由可编程逻辑器件以最小化编程时间的方法
公开(公告)号：US07143384B1
公开(公告)日：2006-11-28
申请号：US10716947
申请日：2003-11-18
申请人： Jay T. Young , Jeffrey V. Lindholm , Sridhar Krishnamurthy
发明人： Jay T. Young , Jeffrey V. Lindholm , Sridhar Krishnamurthy
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5077
摘要： Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.
摘要翻译：将设计路由到可编程逻辑器件（PLD）中以提高将多帧写入（MFW）压缩技术应用于所得配置比特流的有效性的方法。这些方法应用放置模式和/或路由模板，以鼓励在路由设计中包含多个重复的路由路径。复制的路由路径导致重复的配置数据。因此，在PLD中实现路由设计的配置比特流包括复制的配置数据帧的数量，并且非常适合于受益于MFW压缩技术。

3. 发明授权

US07249335B1 Methods of routing programmable logic devices to minimize programming time 失效
标题翻译：路由可编程逻辑器件以最小化编程时间的方法
公开(公告)号：US07249335B1
公开(公告)日：2007-07-24
申请号：US11590132
申请日：2006-10-31
申请人： Jay T. Young , Jeffrey V. Lindholm , Sridhar Krishnamurthy
发明人： Jay T. Young , Jeffrey V. Lindholm , Sridhar Krishnamurthy
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.
摘要翻译：将设计路由到可编程逻辑器件（PLD）中以提高将多帧写入（MFW）压缩技术应用于所得配置比特流的有效性的方法。这些方法应用放置模式和/或路由模板，以鼓励在路由设计中包含多个重复的路由路径。复制的路由路径导致重复的配置数据。因此，在PLD中实现路由设计的配置比特流包括复制的配置数据帧的数量，并且非常适合于受益于MFW压缩技术。

4. 发明授权

US06944809B2 Methods of resource optimization in programmable logic devices to reduce test time 有权
标题翻译：可编程逻辑器件资源优化方法，以减少测试时间
公开(公告)号：US06944809B2
公开(公告)日：2005-09-13
申请号：US10214025
申请日：2002-08-06
申请人： Andrew W. Lai , Randy J. Simmons , Teymour M. Mansour , Vincent L. Tong , Jeffrey V. Lindholm , Jay T. Young , William R. Troxel , Sridhar Krishnamurthy
发明人： Andrew W. Lai , Randy J. Simmons , Teymour M. Mansour , Vincent L. Tong , Jeffrey V. Lindholm , Jay T. Young , William R. Troxel , Sridhar Krishnamurthy
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5054
摘要： Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
摘要翻译：优化可编程逻辑器件（PLD）中路由资源使用的方法，以最小化测试时间。识别出在大多数设计中未使用的一组路由资源，并且向用户提供阻止使用这些资源的设备模型。由于路由资源永远不会被使用，所以不需要由PLD制造商进行测试，从而大大减少测试时间。例如，PLD系列中的每个PLD通常使用不同数量的相似瓦片来设计。因此，家族中较小的PLD包括不必要的大量路由资源。这些过度的路由资源可以在实现设计期间被禁用。在另一示例中，沿着阵列的边缘的每个瓦片包括主要用于提供对不存在的瓦片的访问的布线资源。这些冗余路由资源可以在实现设计期间被禁用。

5. 发明授权

US07149997B1 Routing with frame awareness to minimize device programming time and test cost 有权
标题翻译：具有框架意识的路由，以最小化设备编程时间和测试成本
公开(公告)号：US07149997B1
公开(公告)日：2006-12-12
申请号：US10966643
申请日：2004-10-15
申请人： Jay T. Young , Jeffrey V. Lindholm , Ian L. McEwen
发明人： Jay T. Young , Jeffrey V. Lindholm , Ian L. McEwen
IPC分类号： G06F17/50 , G06F1/24 , G06F9/45
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method of routing a design on a programmable logic device (PLD) includes generating a database that identifies the correspondence between routing resources of the PLD and programming frames of the PLD. A first set of programming frames required to implement the logic of the design is identified, and the cost associated with using the first set of programming frames is eliminated. A second set of programming frames that are not used to implement the logic of the design is also identified, and the cost associated with using the second set of programming frames is maximized. Interconnect networks of the design are then routed, taking into account the costing of the programming frames. When a programming frame from the second set is used, the cost associated with using this programming frame is eliminated. This method minimizes used programming frames and maximizes unused programming frames, thus reducing PLD configuration time.
摘要翻译：在可编程逻辑器件（PLD）上路由设计的方法包括生成识别PLD的路由资源与PLD的编程帧之间的对应关系的数据库。识别实现设计逻辑所需的第一组编程框架，消除与使用第一组编程帧相关联的成本。还识别出不用于实现设计逻辑的第二组编程帧，并且与使用第二组编程帧相关联的成本最大化。然后将设计的互连网络路由，同时考虑到编程帧的成本计算。当使用来自第二组的编程帧时，消除了与使用该编程帧相关联的成本。这种方法最大限度地减少了使用的编程帧并使未使用的编程帧最大化，从而减少了PLD配置时间。

6. 发明授权

US06907595B2 Partial reconfiguration of a programmable logic device using an on-chip processor 有权
标题翻译：使用片上处理器对可编程逻辑器件进行部分重新配置
公开(公告)号：US06907595B2
公开(公告)日：2005-06-14
申请号：US10319051
申请日：2002-12-13
申请人： Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck , Stephen W. Trynosky , Jeffrey V. Lindholm , Trevor J. Bauer
发明人： Derek R. Curd , Punit S. Kalra , Richard J. LeBlanc , Vincent P. Eck , Stephen W. Trynosky , Jeffrey V. Lindholm , Trevor J. Bauer
IPC分类号： G06F15/78 , G06F17/50
CPC分类号： G06F15/7867
摘要： A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.
摘要翻译：使用由处理器控制的读 - 修改 - 写入方案来部分地重新配置可编程逻辑器件，例如现场可编程门阵列。部分重新配置包括（1）将一组配置数据值加载到可编程逻辑器件的配置存储器阵列中，从而配置可编程逻辑器件; （2）从配置存储器阵列读取配置数据值的第一帧; （3）修改配置数据值的第一帧中的配置数据值的子集，由此创建配置数据值的第一修改帧; 和（4）用配置数据值的第一修改帧重写配置存储器阵列中的配置数据值的第一帧，从而部分地重新配置可编程逻辑器件。读取，修改和重写的步骤在处理器的控制下执行。

7. 发明授权

US08001511B1 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 有权
标题翻译：在多产品可编程IC芯片的可选边界实现和建模互连线路的方法
公开(公告)号：US08001511B1
公开(公告)日：2011-08-16
申请号：US12245858
申请日：2008-10-06
申请人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： H03K19/177 , G06F17/5054 , G06F17/5068
摘要： A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
摘要翻译：使用相同的软件模型对两个IC芯片建模的方法，尽管两个芯片包括物理差异。第一可编程逻辑器件（PLD）管芯包括第一和第二部分，并被编码以使第一部分可操作，第二部分不可操作。在两部分之间的边界处，穿过边界的互连线包括第一部分中的第一部分和第二部分中的第二部分。第二PLD管芯包括第一PLD管芯的第一部分，同时省略第二部分。延伸到第二管芯边缘的互连线成对连接在一起。两个芯片的软件模型包括一个省略对耦合的终端模型，增加了对省略连接进行补偿的RC负载，以及（对于双向互连线），标记每对中的一条互连线，因为无法使用路由软件。

8. 发明授权

US07451421B1 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 有权
标题翻译：在多产品可编程IC芯片的可选边界实现和建模互连线路的方法
公开(公告)号：US07451421B1
公开(公告)日：2008-11-11
申请号：US11333865
申请日：2006-01-17
申请人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： G06F9/455 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/177 , G06F17/5054 , G06F17/5068
摘要： A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
摘要翻译：使用相同的软件模型对两个IC芯片建模的方法，尽管两个芯片包括物理差异。第一可编程逻辑器件（PLD）管芯包括第一和第二部分，并被编码以使第一部分可操作，第二部分不可操作。在两部分之间的边界处，穿过边界的互连线包括第一部分中的第一部分和第二部分中的第二部分。第二PLD管芯包括第一PLD管芯的第一部分，同时省略第二部分。延伸到第二管芯边缘的互连线成对连接在一起。两个芯片的软件模型包括一个省略对耦合的终端模型，增加了对省略连接进行补偿的RC负载，以及（对于双向互连线），标记每对中的一条互连线，因为无法使用路由软件。

9. 发明授权

US07107565B1 PLD device representation with factored repeatable tiles 有权
标题翻译： PLD设备表示与因子可重复的瓷砖
公开(公告)号：US07107565B1
公开(公告)日：2006-09-12
申请号：US10627510
申请日：2003-07-25
申请人： Jeffrey V. Lindholm , Keith R. Bean
发明人： Jeffrey V. Lindholm , Keith R. Bean
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Structures and methods of representing programmable PLD hardware tiles including common routing resources common to all of the hardware tiles and unique logic resources unique to each hardware tile. A software representation of the programmable hardware tiles includes a common software tile including a description of the common routing resources, and, for each hardware tile, a unique software tile including a description of the unique logic resources included in the hardware tile. The common software tile has first terminals for coupling an instance of the common software tile to other instances of the common software tile, and also has second terminals. The unique software tile includes terminals for coupling the unique software tile to the second terminals of an instance of the common software tile. The software representation can also include a PLD device model that utilizes a uniform numbering scheme based on numbered instances of the common software tile.
摘要翻译：表示可编程PLD硬件瓦片的结构和方法，包括所有硬件瓦片和每个硬件瓦片独有的唯一逻辑资源共有的公共路由资源。可编程硬件瓦片的软件表示包括公共软件瓦片，其包括公共路由资源的描述，并且对于每个硬件瓦片，包括硬件瓦片中包括的唯一逻辑资源的描述的唯一软件瓦片。公用软件瓦片具有用于将公用软件瓦片的实例耦合到公共软件瓦片的其他实例的第一终端，并且还具有第二终端。唯一的软件瓦片包括用于将唯一软件瓦片耦合到公共软件瓦片的实例的第二终端的终端。软件表示还可以包括使用基于公共软件块的编号实例的统一编号方案的PLD设备模型。

10. 发明授权

US06732347B1 Clock template for configuring a programmable gate array 有权
标题翻译：用于配置可编程门阵列的时钟模板
公开(公告)号：US06732347B1
公开(公告)日：2004-05-04
申请号：US09844054
申请日：2001-04-26
申请人： Nicolas J. Camilleri , Edward S. McGettigan , Kenneth J. Stickney, Jr. , Jeffrey V. Lindholm , Kevin L. Bixler , Raymond Kong
发明人： Nicolas J. Camilleri , Edward S. McGettigan , Kenneth J. Stickney, Jr. , Jeffrey V. Lindholm , Kevin L. Bixler , Raymond Kong
IPC分类号： G06F1750
CPC分类号： G06F1/10 , G06F17/5054
摘要： A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.
摘要翻译：时钟模板包括用于编程可编程门阵列（PGA）的时钟帧的数字编程信息。数字编程信息表示与PGA中的各种设计相对应的多种不同的时钟配置。在一个实施例中，数字节目信息包括用于部分重新配置PGA的比特流。在另一个实施例中，数字节目信息被嵌入至少一个设计的数字节目信息中。还公开了通过利用时钟模板来配置具有不同时钟配置的不同设计的PGA的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式