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1. 发明授权

US07480842B1 Method and apparatus for reducing the number of test designs for device testing 有权
标题翻译：减少设备测试设计数量的方法和设备
公开(公告)号：US07480842B1
公开(公告)日：2009-01-20
申请号：US10892603
申请日：2004-07-16
申请人： Jay T. Young , Ian L. McEwen , Reto Stamm
发明人： Jay T. Young , Ian L. McEwen , Reto Stamm
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/263 , G01R31/31704 , G01R31/318516
摘要： The present invention includes an apparatus and method to optimize a set of test designs to obtain complete coverage while reducing bit stream size for programmable fabric. Test designs are selected that do not result in lost coverage. The method selects a set of test designs, removes the set of test designs, and then determines if coverage is lost. If coverage is lost, the method creates a new set of test designs to test the lost coverage. If the new set of test designs is smaller than the removed set, the new set of test designs is added to the test design suite; otherwise the removed test designs are added back to the test design suite. The decision to add the new test designs or removed test designs is based on a number of criteria including evaluating the number of uniquely tested resources in each test design.
摘要翻译：本发明包括一种用于优化一组测试设计以获得完整覆盖同时减少可编程结构的位流大小的装置和方法。选择的测试设计不会导致覆盖率的损失。该方法选择一组测试设计，删除一组测试设计，然后确定覆盖是否丢失。如果覆盖丢失，该方法将创建一组新的测试设计来测试丢失的覆盖。如果新的一组测试设计小于移除的集合，则将新的测试设计集合添加到测试设计套件中; 否则将删除的测试设计添加回测试设计套件。添加新的测试设计或删除的测试设计的决定基于许多标准，包括评估每个测试设计中唯一测试的资源的数量。

2. 发明授权

US08082535B1 Method and apparatus for testing programmable integrated circuits 有权
标题翻译：用于测试可编程集成电路的方法和装置
公开(公告)号：US08082535B1
公开(公告)日：2011-12-20
申请号：US12364667
申请日：2009-02-03
申请人： Ian L. McEwen , Teymour M. Mansour , Andrew G. Anderson , Reto Stamm
发明人： Ian L. McEwen , Teymour M. Mansour , Andrew G. Anderson , Reto Stamm
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F11/263 , G01R31/318516
摘要： A method of testing an IC generates a test design list of test patterns and produces an arc usage string for each test pattern. The arc usage strings are ranked according to the number of untested arcs in each successive test pattern by comparing each of the remaining arc usage strings against an already-tested arc file to identify the arc usage string (test pattern) having the greatest number of untested arcs. A test sequence list of test patterns ranked in order of the most number of untested arcs to the least number of untested arcs is provided to a tester and the IC is tested in order of the test patterns on the test sequence list.
摘要翻译：测试IC的方法产生测试图案的测试设计列表，并为每个测试模式产生弧线使用字符串。通过将剩余电弧使用字符串中的每一个与已经测试的弧形文件进行比较，以识别具有最大未验证数量的电弧使用字符串（测试图案），根据每个连续测试图案中的未测试弧的数量对电弧使用字符串进行排序弧线将测试图案的测试序列列表按照未测试的最多弧数排列到最少未经测试的弧数，并提供给测试者，并按照测试顺序列表上的测试模式的顺序测试IC。

3. 发明授权

US07234120B1 Fault isolation in a programmable logic device 有权
标题翻译：可编程逻辑器件中的故障隔离
公开(公告)号：US07234120B1
公开(公告)日：2007-06-19
申请号：US10959389
申请日：2004-10-06
申请人： Donald Audley Staab , Ian L. McEwen , Reto Stamm , Phoumra Tan
发明人： Donald Audley Staab , Ian L. McEwen , Reto Stamm , Phoumra Tan
IPC分类号： G06F17/50
CPC分类号： G01R31/318516 , G01R31/318342
摘要： Identification of a faulty net in a design implemented on a programmable logic device (PLD). In one approach, configuration data is generated to implement a duplicate circuit of a failing sub-circuit in the design. The PLD is configured with the configuration data that implements the failing sub-circuit and the duplicate circuit, and at least one set of input signals is applied to the sub-circuit and the duplicate circuit. A signal from each net in the sub-circuit is compared on the PLD to a corresponding net in the duplicate circuit. In response to the signal from the net in the sub-circuit being unequal to a signal from the corresponding net in the duplicate circuit, the net in the sub-circuit is identified as faulty.
摘要翻译：识别在可编程逻辑器件（PLD）上实现的设计中的故障网。在一种方法中，生成配置数据以在设计中实现故障子电路的重复电路。 PLD配置有实现故障子电路和复制电路的配置数据，并且至少一组输入信号被施加到子电路和复制电路。将子电路中的每个网络的信号在PLD上与复制电路中的相应网络进行比较。响应于来自副电路中的网络的信号不等于来自重复电路中的相应网络的信号，子电路中的网络被识别为有故障的。

4. 发明授权

US07949974B1 Isolation verification within integrated circuits 有权
标题翻译：集成电路中的隔离验证
公开(公告)号：US07949974B1
公开(公告)日：2011-05-24
申请号：US12038837
申请日：2008-02-28
申请人： Jason J. Moore , Ian L. McEwen , Reto Stamm , John Damian Corbett , Eric M. Shiflet
发明人： Jason J. Moore , Ian L. McEwen , Reto Stamm , John Damian Corbett , Eric M. Shiflet
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer-implemented method of verifying isolation between a plurality of modules of a circuit design to be implemented within an integrated circuit can include identifying a first module and at least a second module of the circuit design for the integrated circuit. One or more circuit attributes indicative of isolation between the first module and the second module can be identified and compared with at least one isolation criterion. An indication of whether the first module is isolated from the second module can be output according to results of the comparison.
摘要翻译：一种用于验证要在集成电路内实现的电路设计的多个模块之间的隔离的计算机实现的方法可以包括识别用于集成电路的电路设计的第一模块和至少第二模块。可以识别指示第一模块和第二模块之间的隔离的一个或多个电路属性，并与至少一个隔离标准进行比较。可以根据比较结果来输出第一模块是否与第二模块隔离的指示。

5. 发明授权

US08418221B1 Methods of prioritizing routing resources to generate and evaluate test designs in programmable logic devices 有权
标题翻译：优化路由资源以生成和评估可编程逻辑设备中的测试设计的方法
公开(公告)号：US08418221B1
公开(公告)日：2013-04-09
申请号：US10777421
申请日：2004-02-12
申请人： Jay T. Young , Ian L. McEwen
发明人： Jay T. Young , Ian L. McEwen
IPC分类号： G06F21/00
CPC分类号： G01R31/318516 , G01R31/31704 , G06F17/5054 , G06F17/5077
摘要： Methods of prioritizing untested routing resources in programmable logic devices (PLDs) to generate test suites that include a minimal number of test designs. The untested routing resources are prioritized (e.g., placed into an ordered list) based on a number of untested input or output terminals for each untested resource. The number of untested input or output terminals (whichever is larger) for each routing resource determines the minimum number of additional test designs in which the routing resource must be included. The resulting prioritization can be utilized by a router, for example, to first include in test designs those routing resources that must be included in the largest remaining number of test designs. The described prioritization methods can also be used to select one of two or more test designs that should be included in the overall test suite. In each case, the overall number of test designs is reduced.
摘要翻译：在可编程逻辑器件（PLD）中对未经测试的路由资源进行优先级排序以生成包含最少数量的测试设计的测试套件的方法。未经测试的路由资源基于每个未测试资源的未测试的输入或输出终端的数量被优先排列（例如，放置在有序列表中）。每个路由资源的未测试的输入或输出终端数量（以较大者为准）决定必须包含路由资源的其他测试设计的最小数量。所产生的优先级可由路由器利用，例如，首先在测试设计中包括必须包含在最大剩余数量的测试设计中的路由资源。所描述的优先级方法也可用于选择应包括在整个测试套件中的两个或多个测试设计之一。在每种情况下，测试设计的总数减少。

6. 发明授权

US07299430B1 Reducing design execution run time bit stream size for device testing 失效
标题翻译：减少设计执行运行时位流大小进行设备测试
公开(公告)号：US07299430B1
公开(公告)日：2007-11-20
申请号：US11064369
申请日：2005-02-23
申请人： Ian L. McEwen , Jay T. Young
发明人： Ian L. McEwen , Jay T. Young
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G01R31/318519
摘要： A method of testing a programmable logic device (PLD) can include distinguishing between stages within the design that uniquely test a routing resource and stages that do not. The method also can include un-routing at least a portion of the design corresponding to one or more of the stages that do not uniquely test a routing resource. The stage(s) can be excluded from the design. The portion of the design that was un-routed can be re-routed by passing those stages that do not uniquely test a routing resource.
摘要翻译：测试可编程逻辑器件（PLD）的方法可以包括区分设计中唯一测试路由资源的阶段和不进行路由资源的阶段。该方法还可以包括对与不唯一测试路由资源的一个或多个阶段相对应的设计的至少一部分进行解路由。舞台可以从设计中排除。通过传递不唯一测试路由资源的那些阶段，可以重新路由未路由的设计部分。

7. 发明授权

US07149997B1 Routing with frame awareness to minimize device programming time and test cost 有权
标题翻译：具有框架意识的路由，以最小化设备编程时间和测试成本
公开(公告)号：US07149997B1
公开(公告)日：2006-12-12
申请号：US10966643
申请日：2004-10-15
申请人： Jay T. Young , Jeffrey V. Lindholm , Ian L. McEwen
发明人： Jay T. Young , Jeffrey V. Lindholm , Ian L. McEwen
IPC分类号： G06F17/50 , G06F1/24 , G06F9/45
CPC分类号： G06F17/5077 , G06F17/5054
摘要： A method of routing a design on a programmable logic device (PLD) includes generating a database that identifies the correspondence between routing resources of the PLD and programming frames of the PLD. A first set of programming frames required to implement the logic of the design is identified, and the cost associated with using the first set of programming frames is eliminated. A second set of programming frames that are not used to implement the logic of the design is also identified, and the cost associated with using the second set of programming frames is maximized. Interconnect networks of the design are then routed, taking into account the costing of the programming frames. When a programming frame from the second set is used, the cost associated with using this programming frame is eliminated. This method minimizes used programming frames and maximizes unused programming frames, thus reducing PLD configuration time.
摘要翻译：在可编程逻辑器件（PLD）上路由设计的方法包括生成识别PLD的路由资源与PLD的编程帧之间的对应关系的数据库。识别实现设计逻辑所需的第一组编程框架，消除与使用第一组编程帧相关联的成本。还识别出不用于实现设计逻辑的第二组编程帧，并且与使用第二组编程帧相关联的成本最大化。然后将设计的互连网络路由，同时考虑到编程帧的成本计算。当使用来自第二组的编程帧时，消除了与使用该编程帧相关联的成本。这种方法最大限度地减少了使用的编程帧并使未使用的编程帧最大化，从而减少了PLD配置时间。

8. 发明授权

US07058919B1 Methods of generating test designs for testing specific routing resources in programmable logic devices 失效
标题翻译：生成用于测试可编程逻辑器件中特定路由资源的测试设计的方法
公开(公告)号：US07058919B1
公开(公告)日：2006-06-06
申请号：US10696357
申请日：2003-10-28
申请人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
发明人： Jay T. Young , Sridhar Krishnamurthy , Jeffrey V. Lindholm , Ian L. McEwen
IPC分类号： G06F17/50
CPC分类号： G01R31/318516 , G01R31/31704
摘要： Methods of directly targeting specified routing resources in a PLD, e.g., routing resources that need to be tested. Test designs are produced that implement observable nets using the targeted routing resources. A PLD router is used to route from a target routing resource backwards through the routing fabric of the PLD to the source of an observable net. The net is identified based on the source, and loads of the net are identified as router load targets. The router is then used to route from the target routing resource forwards to one of the loads on the net. This process can be repeated for a list of target routing resources to provide a test design that tests as many of the targeted routing resources as possible. Additional test designs can be created to test remaining target routing resources. In other embodiments, the router routes first forwards, then backwards.
摘要翻译：直接针对PLD中的指定路由资源的方法，例如路由需要测试的资源。使用目标路由资源实现可观察网络的测试设计。 PLD路由器用于从目标路由资源向后路由PLD的路由结构到可观察网络的源。网络基于源标识，网络的负载被标识为路由器负载目标。路由器然后用于从目标路由资源转发到网络上的一个负载。可以针对目标路由资源列表重复此过程，以提供尽可能多的目标路由资源的测试设计。可以创建其他测试设计来测试剩余的目标路由资源。在其他实施例中，路由器首先向前路由，然后向后路由。

9. 发明授权

US08117577B1 Determining timing paths within a circuit block of a programmable integrated circuit 有权
标题翻译：确定可编程集成电路的电路块内的定时路径
公开(公告)号：US08117577B1
公开(公告)日：2012-02-14
申请号：US12361516
申请日：2009-01-28
申请人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
发明人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/5031 , G06F2217/84
摘要： A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.
摘要翻译：识别电路块的定时路径的计算机实现的方法可以包括表示包括至少一个可旁路组件的电路块作为具有由节点链接的多个元件的框图。该方法可以包括生成包括框图中每个元素的文本描述的地图文件，其中每个元素的文本描述指定该元素的旁路指示符。该方法还可以包括从地图文件生成多个子路径，根据多个子路径的起始点和终点的共同点选择性地组合多个子路径中的不同子路径，从多个子路径确定定时路径多个子路径，并输出定时路径。

10. 发明授权

US08104011B1 Method of routing a design to increase the quality of the design 有权
标题翻译：路由设计方法以提高设计质量
公开(公告)号：US08104011B1
公开(公告)日：2012-01-24
申请号：US12053504
申请日：2008-03-21
申请人： Prasanna Sundararajan , Carter Hamilton , Ian L. McEwen
发明人： Prasanna Sundararajan , Carter Hamilton , Ian L. McEwen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of circuit design for an integrated circuit (IC) can include identifying a plurality of routing resources, wherein each of the plurality of routing resources is associated with a reliability measure, and selecting routing resources for use in routing a circuit design for the according to, at least in part, the reliability measures. The circuit design for the can be routed using the selected routing resources.
摘要翻译：一种用于集成电路（IC）的电路设计方法可以包括识别多个路由资源，其中多个路由资源中的每一个与可靠性度量相关联，并且选择路由资源用于路由选择相应的电路设计至少部分是可靠性措施。可以使用所选择的路由资源路由电路设计。

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