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1. 发明授权

US08117577B1 Determining timing paths within a circuit block of a programmable integrated circuit 有权
标题翻译：确定可编程集成电路的电路块内的定时路径
公开(公告)号：US08117577B1
公开(公告)日：2012-02-14
申请号：US12361516
申请日：2009-01-28
申请人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
发明人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/5031 , G06F2217/84
摘要： A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.
摘要翻译：识别电路块的定时路径的计算机实现的方法可以包括表示包括至少一个可旁路组件的电路块作为具有由节点链接的多个元件的框图。该方法可以包括生成包括框图中每个元素的文本描述的地图文件，其中每个元素的文本描述指定该元素的旁路指示符。该方法还可以包括从地图文件生成多个子路径，根据多个子路径的起始点和终点的共同点选择性地组合多个子路径中的不同子路径，从多个子路径确定定时路径多个子路径，并输出定时路径。

2. 发明授权

US07284228B1 Methods of using ant colony optimization to pack designs into programmable logic devices 有权
标题翻译：使用蚁群优化将设计包装到可编程逻辑器件中的方法
公开(公告)号：US07284228B1
公开(公告)日：2007-10-16
申请号：US11184452
申请日：2005-07-19
申请人： Philip R. Haratsaris
发明人： Philip R. Haratsaris
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5009 , G06F17/504 , G06F17/5054 , G06F2217/10 , G06F2217/84
摘要： Methods of packing a design into a programmable logic device (PLD) using ant colony optimization. An augmented graph is assigned to the design, e.g., nodes and edges are defined based on sub-circuits and interconnections in the design, and a topological order is assigned to the nodes. An equation is determined for probabilistic behavior of packing agents at each node, and an initial pheromone value is assigned to each edge. In each iteration, each of “M” packing agents makes a tour of the graph, with merging decisions being made at each node in a probabilistic manner determined by the equation and pheromone values. The M resulting packing implementations are scored, and the best packing implementation is used to change the pheromone values for the next iteration. The probabilistic equation and scoring can be based on timing, area, and/or power constraints, for example. The process is complete when predefined criteria are met.
摘要翻译：使用蚁群优化将设计打包成可编程逻辑器件（PLD）的方法。扩展图被分配给设计，例如，基于设计中的子电路和互连来定义节点和边缘，并且将拓扑顺序分配给节点。确定每个节点上包装剂概率行为的方程，并将每个边缘分配初始信息素值。在每次迭代中，每个“M”包装代理进行图形的浏览，其中以由方程和信息素值确定的概率方式在每个节点进行合并确定。对所得到的M包装实施进行评分，并且使用最佳包装实施来改变下一次迭代的信息素值。概率方程和评分可以基于例如时间，面积和/或功率约束。当满足预定义的标准时，该过程完成。

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