专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06673652B1 Underfilling method for a flip-chip packaging process 失效
标题翻译：倒装芯片封装工艺的底部填充方法
公开(公告)号：US06673652B1
公开(公告)日：2004-01-06
申请号：US09128226
申请日：1998-08-03
申请人： Jao-Chin Cheng , Ming-Hsien Chen
发明人： Jao-Chin Cheng , Ming-Hsien Chen
IPC分类号： H01L2144
CPC分类号： H01L21/563 , H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/73203 , H01L2224/81203 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/29099 , H01L2924/00 , H01L2224/05599
摘要： An underfilling method for a flip-chip packaging process includes coating a underfill material layer over bumps on a semiconductor substrate, performing a die sawing process on the semiconductor substrate to from a number of dies, and performing a flip-chip process on each of the dies to adhere each of the dies to another substrate. Because the underfill material is coated from the top of the bumps, the air-trapping problem can be eliminated. The process time is shortened to improve yield because the underfill material is dispensed over all the dies before the die-sawing process. This is different from the conventional underfilling process, which has to dispense underfill material and seal edges on each individual die.
摘要翻译：用于倒装芯片封装工艺的底部填充方法包括在半导体衬底上的凸块上涂覆底部填充材料层，对半导体衬底进行模具切割处理以从多个裸片上进行倒装芯片处理，将每个管芯粘附到另一个基底上。因为底部填充材料是从凸起的顶部涂覆的，所以可以消除空气捕获问题。缩短处理时间以提高产量，因为在模切工艺之前将底部填充材料分配在所有模具上。这与传统的填充过程不同，后处理过程必须在每个单独的模具上分配底部填充材料和密封边缘。

2. 发明授权

US06384613B1 Wafer burn-in testing method 失效
标题翻译：晶圆老化测试方法
公开(公告)号：US06384613B1
公开(公告)日：2002-05-07
申请号：US09064264
申请日：1998-04-22
申请人： Jao-Chin Cheng , Ming-Hsien Chen
发明人： Jao-Chin Cheng , Ming-Hsien Chen
IPC分类号： G01R3102
CPC分类号： G01R31/2856 , G01R31/2862
摘要： A method for burn-in testing a complete wafer comprising the steps of first providing a wafer, and then forming a plurality of bumps thereon. Next, a tape-automated bonding tape having a plurality of bonding pads is designed and fabricated, wherein each bonding pad includes a corresponding circuit and an external contact point. Then, electrical connections between the bonding pads and the bumps are made and a plurality of voltages and currents are supplied through the tape-automated bonding tape for carrying out burn-in tests. Bum-in tests are performed for the whole wafer. Defective chips are singled out after the wafer is cut up and only good chips are used for subsequent packaging. Therefore, production cost can be saved and packaging yield can be increased. Furthermore, a multiple circuit layers design can be employed to fabricate the tape-automated bonding tape. Consequently, circuits necessary for carrying out the burn-in test for the whole wafer is simplified.
摘要翻译：一种用于老化测试完整晶片的方法，包括以下步骤：首先提供晶片，然后在其上形成多个凸块。接下来，设计并制造具有多个接合焊盘的带自动化接合带，其中每个接合焊盘包括相应的电路和外部接触点。然后，形成接合焊盘和凸块之间的电连接，并且通过带自动化粘合带供给多个电压和电流，以进行老化测试。对整个晶片进行Bum-in测试。在切割晶片之后，选择出缺陷的芯片，并且仅将好的芯片用于随后的封装。因此，可以节省生产成本，并且可以提高包装产量。此外，可以采用多电路层设计来制造带自动化粘合带。因此，简化了对整个晶片进行老化测试所需的电路。

3. 发明授权

US06709897B2 Method of forming IC package having upward-facing chip cavity 有权
标题翻译：形成具有向上的芯片腔的IC封装的方法
公开(公告)号：US06709897B2
公开(公告)日：2004-03-23
申请号：US10050074
申请日：2002-01-15
申请人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
发明人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
IPC分类号： H01L2144
CPC分类号： H01L23/49822 , H01L23/13 , H01L23/142 , H01L24/24 , H01L24/82 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05024 , H01L2224/05548 , H01L2224/05569 , H01L2224/12105 , H01L2224/24246 , H01L2224/24247 , H01L2224/32245 , H01L2224/45144 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/92244 , H01L2924/01075 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2224/24227 , H01L2924/00
摘要： A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. By forming a patterned dielectric layer to expose bonding pads on a silicon chip and subsequently connecting the bonding pad on the chip with trace lines on the substrate through electroplating, reliable connections between the chip and substrate are formed and no more bubbles are formed inside the dielectric layer.
摘要翻译：一种形成具有朝上的芯片空腔的集成电路封装的方法，使得基板的制造和硅芯片的封装被组合。通过形成图案化的电介质层以暴露硅芯片上的焊盘，随后通过电镀将衬底上的接合焊盘与衬底上的迹线连接，形成芯片和衬底之间的可靠连接，并且在电介质内不再形成气泡层。

4. 发明授权

US06749737B2 Method of fabricating inter-layer solid conductive rods 有权
标题翻译：制造层间固体导电棒的方法
公开(公告)号：US06749737B2
公开(公告)日：2004-06-15
申请号：US09927723
申请日：2001-08-10
申请人： Jao-Chin Cheng , Chang-Chin Hsieh , Chih-Peng Fan , Chih-Hao Yeh
发明人： Jao-Chin Cheng , Chang-Chin Hsieh , Chih-Peng Fan , Chih-Hao Yeh
IPC分类号： C25D502
CPC分类号： H05K3/423 , C25D1/003 , H05K3/0035 , H05K3/4602 , H05K2201/0355 , H05K2201/0394 , H05K2203/025 , H05K2203/0554 , H05K2203/0733
摘要： A method of forming a solid inter-layer conductive rod. A printed circuit board comprising an insulating core layer, a first conductive layer and a second conductive layer is provided. The insulating core layer is sandwiched between the first conductive layer and the second conductive layer. A first opening that exposes a portion of the insulating core layer is formed in the first conductive layer. The exposed insulating core layer is removed by laser drilling to form a second opening that exposes a portion of the second conductive layer. An electroplating process is conducted using the second conductive layer as a negative electrode so that conductive material solidly fills the first opening and the second opening to form a solid conductive rod.
摘要翻译：形成固体层间导电棒的方法。提供了包括绝缘芯层，第一导电层和第二导电层的印刷电路板。绝缘芯层夹在第一导电层和第二导电层之间。在第一导电层中形成露出绝缘芯层的一部分的第一开口。暴露的绝缘芯层通过激光钻孔去除以形成露出第二导电层的一部分的第二开口。使用第二导电层作为负极进行电镀工艺，使得导电材料牢固地填充第一开口和第二开口以形成固体导电棒。

5. 发明授权

US06506633B1 Method of fabricating a multi-chip module package 有权
标题翻译：制造多芯片模块封装的方法
公开(公告)号：US06506633B1
公开(公告)日：2003-01-14
申请号：US10078212
申请日：2002-02-15
申请人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
发明人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
IPC分类号： H01L2144
CPC分类号： H01L25/50 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2221/68377 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/24225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/82001 , H01L2224/82039 , H01L2224/97 , H01L2225/0651 , H01L2225/06524 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A method of fabricating a multi-chip module (MCM) package that can fabricate the substrate and the package simultaneously. The bonding pads of a chip are exposed by forming a patterned dielectric layer, and the bonding pads of the chip are electrically connected to the substrate by utilizing to an electroplating to form a metal layer. The present invention provides a fabircating method that can prevent air bubble produced in the patterned dielectric layer and improve the connection ability between the chip and the substrate.
摘要翻译：一种制造可以同时制造衬底和封装的多芯片模块（MCM）封装的方法。芯片的焊盘通过形成图案化的介电层而被曝光，芯片的焊盘通过利用电镀而与基板电连接以形成金属层。本发明提供一种能够防止在图案化电介质层中产生的气泡并提高芯片与基板之间的连接能力的制造方法。

6. 发明授权

US06506632B1 Method of forming IC package having downward-facing chip cavity 有权
标题翻译：形成具有向下的芯片腔的IC封装的方法
公开(公告)号：US06506632B1
公开(公告)日：2003-01-14
申请号：US10078211
申请日：2002-02-15
申请人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
发明人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
IPC分类号： H01L2144
CPC分类号： H01L24/82 , H01L21/568 , H01L21/6835 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/97 , H01L2224/45144 , H01L2224/73267 , H01L2224/82005 , H01L2224/82039 , H01L2224/82047 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2924/00
摘要： A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating. The adhesive tape is removed. The metallic layer and the conductive layer are patterned. A patterned solder resistant layer is formed over the metallic layer and the conductive layer. The patterned solder resistant layer has a plurality of openings that expose a portion of the conductive layer. A solder ball implant is conducted to form electrical connection between the solder balls and the conductive layer.
摘要翻译：一种形成具有朝下的芯片腔的集成电路封装的方法。提供了包括绝缘芯层和导电层的衬底。在基板中形成通孔，并且在导电层的表面上附着粘合带。硅芯片附着在第一开口底部的暴露的胶带表面上。芯片具有活性表面和背面。所述芯片还包括在所述有源表面上的多个接合焊盘。芯片的背面附着在胶带上。形成图案化的介电层，填充第一开口并覆盖粘合带，活性表面，接合焊盘和绝缘芯层的一部分。图案化电介质层具有暴露接合焊盘和一些通孔的多个开口。通过电镀在开口的暴露表面和图案化电介质层的上表面上形成金属层。去除胶带。金属层和导电层被图案化。在金属层和导电层之上形成图案化的阻焊层。图案化的阻焊层具有暴露导电层的一部分的多个开口。导电焊球植入物以形成焊球和导电层之间的电连接。

7. 发明授权

US06448170B1 Method of producing external connector for substrate 有权
标题翻译：制造基板外部连接器的方法
公开(公告)号：US06448170B1
公开(公告)日：2002-09-10
申请号：US09998453
申请日：2001-11-27
申请人： Jao-Chin Cheng , Chang-Chin Hsieh , Bang-Chiung Liu , Chung-Yuan Chiu
发明人： Jao-Chin Cheng , Chang-Chin Hsieh , Bang-Chiung Liu , Chung-Yuan Chiu
IPC分类号： H01L2144
CPC分类号： H05K3/28 , H01L21/4853 , H05K3/243 , H05K2201/0367 , H05K2203/0542
摘要： A method of producing an external connector is provided. A substrate is provided and a plurality of pads are formed on the substrate. A copper layer is formed on the substrate to cover the pads. A patterned photoresist is formed on the copper layer. The patterned photoresist has a plurality of openings to expose the copper layer which corresponds to the pads. Then, a conductive plug is formed on the exposed copper layer. The patterned photoresist is removed, and the copper layer which is not covered by the conductive plug is subsequently removed. A solder resist is formed over the substrate to cover the pads and the conductive plug. A portion of the solder resist is removed until the conductive plug is exposed, wherein the solder resist is as high as the conductive plug.
摘要翻译：提供一种制造外部连接器的方法。提供衬底并且在衬底上形成多个衬垫。在衬底上形成铜层以覆盖衬垫。在铜层上形成图案化的光致抗蚀剂。图案化的光致抗蚀剂具有多个开口以暴露对应于焊盘的铜层。然后，在暴露的铜层上形成导电塞。去除图案化的光致抗蚀剂，随后去除未被导电塞覆盖的铜层。在衬底上形成阻焊剂以覆盖焊盘和导电插头。去除阻焊剂的一部分直到导电插头露出，其中阻焊层与导电插塞一样高。

8. 发明授权

US06395633B1 Method of forming micro-via 有权
标题翻译：形成微孔的方法
公开(公告)号：US06395633B1
公开(公告)日：2002-05-28
申请号：US09871206
申请日：2001-05-31
申请人： Jao-Chin Cheng , Chang-Chin Hsieh , Chih-Peng Fan , Chin-Chung Chang
发明人： Jao-Chin Cheng , Chang-Chin Hsieh , Chih-Peng Fan , Chin-Chung Chang
IPC分类号： H01L2144
CPC分类号： H05K3/4647 , H05K3/108 , H05K3/243 , H05K2203/0542 , H05K2203/0733
摘要： A method of forming a micro-via, for fabrication and design of a layout of a circuit board. A patterned conductive wiring layer is formed on the substrate. A copper layer is plated onto the substrate and the conductive wiring layer. A photoresist layer is formed on the copper layer. A part of the photoresist layer is removed to expose a part of the copper layer. Using the copper layer as a seed layer, a conductive pillar is formed on the exposed part of the copper layer. The photoresist layer is removed. The exposed plated copper layer is removed. An insulation layer is formed on surfaces of the substrate and the conductive pillar. A part of the insulation layer is removed to expose the conductive pillar. A patterned conductive wiring layer is formed on the conductive pillar.
摘要翻译：一种形成微通孔的方法，用于制造和设计电路板的布局。在基板上形成有图案的导电布线层。将铜层镀在基板和导电布线层上。在铜层上形成光致抗蚀剂层。去除光致抗蚀剂层的一部分以露出铜层的一部分。使用铜层作为种子层，在铜层的露出部分上形成导电柱。去除光致抗蚀剂层。暴露的镀铜层被去除。在基板和导电柱的表面上形成绝缘层。去除绝缘层的一部分以露出导电柱。在导电柱上形成有图案的导电布线层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式