专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10249636B2 Vertical memory devices and methods of manufacturing the same 有权
公开(公告)号：US10249636B2
公开(公告)日：2019-04-02
申请号：US15692606
申请日：2017-08-31
申请人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
发明人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
IPC分类号： H01L27/1157 , H01L23/522 , H01L23/528 , H01L27/11582 , H01L27/11565
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

2. 发明授权

US09786676B2 Vertical memory devices and methods of manufacturing the same 有权
公开(公告)号：US09786676B2
公开(公告)日：2017-10-10
申请号：US15217313
申请日：2016-07-22
申请人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
发明人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
IPC分类号： H01L27/115 , H01L27/1157 , H01L27/11582 , H01L23/522 , H01L23/528
CPC分类号： H01L27/1157 , H01L23/5226 , H01L23/528 , H01L27/11565 , H01L27/11582
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

3. 发明授权

US09859296B2 Semiconductor devices including a conductive pattern contacting a channel pattern and methods of manufacturing the same 有权
公开(公告)号：US09859296B2
公开(公告)日：2018-01-02
申请号：US15160335
申请日：2016-05-20
申请人： Se-Jun Park , Jang-Gn Yun , Sung-Min Hwang , Ahn-Sik Moon , Zhiliang Xia
发明人： Se-Jun Park , Jang-Gn Yun , Sung-Min Hwang , Ahn-Sik Moon , Zhiliang Xia
IPC分类号： H01L29/792 , H01L27/1157 , H01L27/11582
CPC分类号： H01L27/1157 , H01L27/11582
摘要： A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

4. 发明申请

US20170069636A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20170069636A1
公开(公告)日：2017-03-09
申请号：US15160335
申请日：2016-05-20
申请人： Se-Jun PARK , Jang-Gn Yun , Sung-Min Hwang , Ahn-Sik Moon , Zhiliang Xia
发明人： Se-Jun PARK , Jang-Gn Yun , Sung-Min Hwang , Ahn-Sik Moon , Zhiliang Xia
IPC分类号： H01L27/115 , H01L23/528 , H01L21/768 , H01L23/522
CPC分类号： H01L27/1157 , H01L27/11582
摘要： A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.
摘要翻译：一种半导体器件包括多个绝缘图案和多个栅极交替重复堆叠在基板上，沟道图案沿基本上垂直于基板顶表面的第一方向延伸穿过栅极，沟道图案和衬底，以及沟道图案和半导体图案之间的导电图案。导电图案将沟道图案电连接到半导体图案。导电图案接触通道图案的底部边缘和半导体图案的上表面。

5. 发明授权

US09899394B2 Vertical memory devices having contact plugs contacting stacked gate electrodes 有权
公开(公告)号：US09899394B2
公开(公告)日：2018-02-20
申请号：US15001877
申请日：2016-01-20
申请人： Sung-Min Hwang , Jee-Yong Kim , Dae-Seok Byeon
发明人： Sung-Min Hwang , Jee-Yong Kim , Dae-Seok Byeon
IPC分类号： H01L27/115 , H01L27/11578 , H01L27/11575 , H01L27/11573 , H01L27/11565 , H01L27/1157 , H01L27/11563 , H01L27/11582
CPC分类号： H01L27/115 , H01L27/11563 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.

6. 发明授权

US09431420B2 Semiconductor devices including vertical cell strings that are commonly connected 有权
标题翻译：包括通常连接的垂直单元串的半导体器件
公开(公告)号：US09431420B2
公开(公告)日：2016-08-30
申请号：US14728574
申请日：2015-06-02
申请人： Sung-Min Hwang
发明人： Sung-Min Hwang
IPC分类号： H01L27/115 , G11C16/04 , G11C16/12 , G11C16/34
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/12 , G11C16/3427 , G11C2216/02 , H01L27/11565 , H01L27/11573
摘要： A semiconductor device includes bit lines on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel structures connecting the bit lines to the common source line. Each of the channel structures may include a plurality of first vertical portions penetrating the gate structure and being connected to the bit lines, a second vertical portion penetrating the gate structure and being connected to the common source line, and a horizontal portion provided between the substrate and the gate structure to connect the first and second vertical portions to each other.
摘要翻译：半导体器件包括衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线以及将位线连接到公共源极线的沟道结构。每个通道结构可以包括穿过栅极结构并连接到位线的多个第一垂直部分，穿过栅极结构并连接到公共源极线的第二垂直部分，以及设置在基板之间的水平部分以及将第一和第二垂直部彼此连接的栅极结构。

7. 发明授权

US08729622B2 Three dimensional semiconductor memory devices and methods of fabricating the same 有权
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US08729622B2
公开(公告)日：2014-05-20
申请号：US13276682
申请日：2011-10-19
申请人： Hui-Chang Moon , Sung-Min Hwang , Woonkyung Lee
发明人： Hui-Chang Moon , Sung-Min Hwang , Woonkyung Lee
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/11556 , H01L29/7926
摘要： A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.
摘要翻译：三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。第一串选择栅极设置在单元栅极的最上面的单元栅极上。每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。第一补充导电图案与第一串选择门之一的侧壁接触。

8. 发明授权

US08592912B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08592912B2
公开(公告)日：2013-11-26
申请号：US13106481
申请日：2011-05-12
申请人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jae-Joo Shim
发明人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jae-Joo Shim
IPC分类号： H01L29/78
CPC分类号： H01L27/0207 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括：多个导电图案，其堆叠在基板上并彼此间隔开;以及焊盘图案，其包括从多个导电图案中的任一个的一端平行于基板延伸的平坦部分，以及从所述平坦部分的顶表面向上延伸的着陆侧壁部分，其中所述着陆侧壁部分在平行于所述基板并且垂直于所述第一方向的第二方向上的一部分的宽度小于所述平坦部分的宽度。

9. 发明申请

US20130168800A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130168800A1
公开(公告)日：2013-07-04
申请号：US13717803
申请日：2012-12-18
申请人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
发明人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
IPC分类号： H01L29/06
CPC分类号： H01L29/0657 , H01L27/0207 , H01L27/1157 , H01L27/11582
摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
摘要翻译：提供了包括设置在基板上的第一和第二隔离图案的半导体器件。交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

10. 发明申请

US20130143088A1 ELECTRODE ASSEMBLY OF NOVEL STRUCTURE AND PROCESS FOR PREPARATION OF THE SAME 有权
标题翻译：新型结构的电极组件及其制备方法
公开(公告)号：US20130143088A1
公开(公告)日：2013-06-06
申请号：US13582250
申请日：2011-03-31
申请人： Jihoon Cho , Dongmyung Kim , Kiwoong Kim , Sung-Min Hwang , Hyun-Chul Jung , Sungjin Kwon , Hyeong Kim , Ki Hong Min
发明人： Jihoon Cho , Dongmyung Kim , Kiwoong Kim , Sung-Min Hwang , Hyun-Chul Jung , Sungjin Kwon , Hyeong Kim , Ki Hong Min
IPC分类号： H01M10/04
CPC分类号： H01M10/0431 , H01M2/021 , H01M2/0212 , H01M2/1653 , H01M2/1686 , H01M2/18 , H01M2/34 , H01M10/0436 , H01M10/0525 , H01M10/058 , Y02E60/122 , Y02P70/54 , Y10T29/49204
摘要： Disclosed herein is an electrode assembly of a cathode/separator/anode structure, wherein a plurality of first unit electrodes and a second electrode sheet are wound so that the first unit electrodes are opposite to the second electrode sheet via a separator sheet, and a first electrode and a second electrode have opposite polarities.
摘要翻译：本文公开了一种阴极/隔板/阳极结构的电极组件，其中缠绕多个第一单元电极和第二电极片，使得第一单元电极经由隔离片与第二电极片相对，并且第一电极和第二电极具有相反的极性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式