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1. 发明授权

US09209244B2 Semiconductor device with vertical structures that penetrate conductive patterns and interlayer insulating patterns 有权
标题翻译：具有穿透导电图案和层间绝缘图案的垂直结构的半导体器件
公开(公告)号：US09209244B2
公开(公告)日：2015-12-08
申请号：US13717803
申请日：2012-12-18
申请人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
发明人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
IPC分类号： H01L29/06 , H01L27/02 , H01L27/115
CPC分类号： H01L29/0657 , H01L27/0207 , H01L27/1157 , H01L27/11582
摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
摘要翻译：提供了包括设置在基板上的第一和第二隔离图案的半导体器件。交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

2. 发明申请

US20130168800A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130168800A1
公开(公告)日：2013-07-04
申请号：US13717803
申请日：2012-12-18
申请人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
发明人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
IPC分类号： H01L29/06
CPC分类号： H01L29/0657 , H01L27/0207 , H01L27/1157 , H01L27/11582
摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
摘要翻译：提供了包括设置在基板上的第一和第二隔离图案的半导体器件。交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

3. 发明申请

US20120322252A1 SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY 有权
标题翻译：包含三维存储器单元阵列的半导体存储器件
公开(公告)号：US20120322252A1
公开(公告)日：2012-12-20
申请号：US13594102
申请日：2012-08-24
申请人： Byoungkeun SON , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun SON , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

4. 发明授权

US08787082B2 Semiconductor memory device comprising three-dimensional memory cell array 有权
标题翻译：包括三维存储单元阵列的半导体存储器件
公开(公告)号：US08787082B2
公开(公告)日：2014-07-22
申请号：US13594102
申请日：2012-08-24
申请人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： G11C16/04
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

5. 发明授权

US08519472B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08519472B2
公开(公告)日：2013-08-27
申请号：US12831728
申请日：2010-07-07
申请人： Jaehun Jeong , Ju-Young Lim , Hansoo Kim , Jaehoon Jang , Sunil Shim , Jae-Joo Shim
发明人： Jaehun Jeong , Ju-Young Lim , Hansoo Kim , Jaehoon Jang , Sunil Shim , Jae-Joo Shim
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11582
摘要： A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.
摘要翻译：半导体器件包括堆叠栅结构，其包括多个单元栅极图案和交替层叠在半导体衬底上并沿第一方向延伸的绝缘图案。有源图案和栅极电介质图案设置在堆叠栅极结构中。有源图案穿透层叠栅极结构并且在与第一方向相交的第二方向上彼此间隔开，并且栅极电介质图案插入在单元栅极图案和有源图案之间并且延伸到第一方向的上表面和下表面单元格栅格图案。有源图案共享堆叠栅极结构中的单元栅极图案。

6. 发明授权

US08284601B2 Semiconductor memory device comprising three-dimensional memory cell array 有权
标题翻译：包括三维存储单元阵列的半导体存储器件
公开(公告)号：US08284601B2
公开(公告)日：2012-10-09
申请号：US12752485
申请日：2010-04-01
申请人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： G11C16/04
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底，垂直于衬底的存储器串，存储串包括多个存储单元，以及多个细长字线，每个字线包括基本上平行于衬底的第一部分，到存储器串和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线中的第一组电连接到设置在存储器串的第一侧的第一导电线，以及第二组多个字线的组电连接到设置在存储器串的第二侧的第二导线。

7. 发明申请

US20120061744A1 THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20120061744A1
公开(公告)日：2012-03-15
申请号：US13229136
申请日：2011-09-09
申请人： SUNG-MIN HWANG , Hansoo Kim , Changseok Kang , Wonseok Cho , Jae-Joo Shim
发明人： SUNG-MIN HWANG , Hansoo Kim , Changseok Kang , Wonseok Cho , Jae-Joo Shim
IPC分类号： H01L27/105
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11582
摘要： Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.
摘要翻译：提供三维半导体存储器件。三维半导体存储器件包括顺序层叠在基板上的第一堆叠结构和第二堆叠结构。第一堆叠结构包括在衬底上交替重复堆叠的第一绝缘图案和第一栅极图案，并且第二堆叠结构包括在第一堆叠结构上交替重复堆叠的第二绝缘图案和第二栅极图案。多个第一垂直有源图案穿透第一堆叠结构，并且多个第二垂直有源图案穿透第二堆叠结构。第一垂直有源图案的数量大于第二垂直有效图案的数量。

8. 发明申请

US20110012189A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20110012189A1
公开(公告)日：2011-01-20
申请号：US12831728
申请日：2010-07-07
申请人： Jaehun Jeong , Ju-Young Lim , Hansoo Kim , Jaehoon Jang , Sunil Shim , Jae-Joo Shim
发明人： Jaehun Jeong , Ju-Young Lim , Hansoo Kim , Jaehoon Jang , Sunil Shim , Jae-Joo Shim
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11582
摘要： A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.
摘要翻译：半导体器件包括堆叠栅结构，其包括多个单元栅极图案和交替层叠在半导体衬底上并沿第一方向延伸的绝缘图案。有源图案和栅极电介质图案设置在堆叠栅极结构中。有源图案穿透层叠栅极结构并且在与第一方向相交的第二方向上彼此间隔开，并且栅极电介质图案插入在单元栅极图案和有源图案之间并且延伸到第一方向的上表面和下表面单元格栅格图案。有源图案共享堆叠栅极结构中的单元栅极图案。

9. 发明申请

US20100254191A1 SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY 有权
标题翻译：包含三维存储器单元阵列的半导体存储器件
公开(公告)号：US20100254191A1
公开(公告)日：2010-10-07
申请号：US12752485
申请日：2010-04-01
申请人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun Son , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： G11C16/02 , H01L21/3205
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 以及多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上方延伸的第二部分，其中多个字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

10. 发明授权

US08921918B2 Three-dimensional semiconductor devices 有权
标题翻译：三维半导体器件
公开(公告)号：US08921918B2
公开(公告)日：2014-12-30
申请号：US13280759
申请日：2011-10-25
申请人： Jae-Joo Shim , Kyoung-Hoon Kim , Woonkyung Lee , Wonseok Cho , Hoosung Cho , Jintaek Park , Jong-Yeon Kim , Sung-Min Hwang
发明人： Jae-Joo Shim , Kyoung-Hoon Kim , Woonkyung Lee , Wonseok Cho , Hoosung Cho , Jintaek Park , Jong-Yeon Kim , Sung-Min Hwang
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.
摘要翻译：可以提供三维半导体器件。这些装置可以包括包括栅极图案和绝缘图案的堆叠结构。堆叠结构还可以包括第一部分和第二部分，并且堆叠结构的第二部分可以具有比第一部分更窄的宽度。装置还可以包括穿透堆叠结构的活动图案。所述装置还可以包括与堆栈结构相邻的公共源区。所述装置还可以包括在公共源区上的捆扎接触塞。

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