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1. 发明授权

US08896123B2 Nonvolatile memory devices having a three dimensional structure 有权
标题翻译：具有三维结构的非易失性存储器件
公开(公告)号：US08896123B2
公开(公告)日：2014-11-25
申请号：US13478482
申请日：2012-05-23
申请人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
发明人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
IPC分类号： H01L27/115 , H01L23/522 , H01L29/792 , H01L29/94
CPC分类号： H01L27/11578 , H01L27/115 , H01L27/11517 , H01L27/11565 , H01L27/11582
摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
摘要翻译：具有三维结构的非易失性存储装置。非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

2. 发明授权

US08873294B2 Nonvolatile memory devices, erasing methods thereof and memory systems including the same 有权
标题翻译：非易失性存储器件，其擦除方法和包括其的存储器系统
公开(公告)号：US08873294B2
公开(公告)日：2014-10-28
申请号：US13295335
申请日：2011-11-14
申请人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
发明人： Sunil Shim , Jaehoon Jang , Jungdal Choi , Woonkyung Lee , Kihyun Kim
IPC分类号： G11C16/16 , G11C16/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , H01L29/792 , G11C16/30 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.
摘要翻译：提供了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。所述擦除方法包括将地电压施加到与所述电池串的地选择晶体管连接的接地选择线; 将接地电压施加到与电池串的选择晶体管连接的串选择线; 对与单元串的存储单元连接的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

3. 发明授权

US08576629B2 Operating method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US08576629B2
公开(公告)日：2013-11-05
申请号：US13315523
申请日：2011-12-09
申请人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线多个第一选择线。

4. 发明申请

US20130182502A1 Operating Methods of Nonvolatile Memory Devices 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US20130182502A1
公开(公告)日：2013-07-18
申请号：US13784969
申请日：2013-03-05
申请人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
发明人： Byeong-in Cheo , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
IPC分类号： G11C16/14 , G11C7/14
CPC分类号： G11C16/14 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings; floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。所述方法可以包括将字线擦除电压施加到连接到所述多个单元串的存储单元的字线; 连接到多个单元串的接地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

5. 发明授权

US08488402B2 Nonvolatile memory device and method of reading the same using different precharge voltages 有权
标题翻译：非易失性存储器件以及使用不同的预充电电压来读取它们的方法
公开(公告)号：US08488402B2
公开(公告)日：2013-07-16
申请号：US13280421
申请日：2011-10-25
申请人： Sunil Shim , Woonkyung Lee , Jaehoon Jang , Kihyun Kim
发明人： Sunil Shim , Woonkyung Lee , Jaehoon Jang , Kihyun Kim
IPC分类号： G11C11/34 , G11C16/04 , G11C7/10
CPC分类号： G11C7/12 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C2216/14 , H01L27/0688 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, multiple doping regions, multiple cell strings and multiple page buffers. The doping regions extend in a first direction along the substrate and are spaced apart from one another in a second direction. The cell strings are provided according to a specific pattern between adjacent first and second doping regions among the multiple regions, each of the cell strings including multiple cell transistors stacked in a third direction perpendicular to the substrate. The page buffers are connected to the cell strings through bit lines, the page buffers being configured to provide precharge voltages to the bit lines during a read operation. Levels of the precharge voltages provided to the bit lines vary depending on distances between the cell strings and at least one of the first and second doping regions, respectively.
摘要翻译：非易失性存储器件包括衬底，多个掺杂区域，多个单元串和多页缓冲器。掺杂区域沿着衬底在第一方向上延伸并且在第二方向上彼此间隔开。根据多个区域中的相邻的第一和第二掺杂区域之间的特定图案提供单元串，每个单元串包括在与基板垂直的第三方向上堆叠的多个单元晶体管。页缓冲器通过位线连接到单元串，页缓冲器被配置为在读操作期间向位线提供预充电电压。提供给位线的预充电电压的电平分别根据电池串与第一和第二掺杂区域中的至少一个之间的距离而变化。

6. 发明申请

US20130171806A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20130171806A1
公开(公告)日：2013-07-04
申请号：US13779334
申请日：2013-02-27
申请人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
发明人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
IPC分类号： H01L21/02
CPC分类号： H01L21/02365 , H01L21/02697 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.
摘要翻译：提供一种三维半导体存储器件。三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

7. 发明授权

US08394716B2 Methods of manufacturing three-dimensional semiconductor devices and related devices 有权
标题翻译：制造三维半导体器件及相关器件的方法
公开(公告)号：US08394716B2
公开(公告)日：2013-03-12
申请号：US12963241
申请日：2010-12-08
申请人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang
发明人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang
IPC分类号： H01L21/44
CPC分类号： H01L21/768 , H01L23/5226 , H01L27/11526 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.
摘要翻译：三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面离衬底更远。多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。还讨论了相关方法。

8. 发明授权

US08278170B2 Methods of forming nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein 有权
标题翻译：形成其中具有垂直集成的非易失性存储单元子串的非易失性存储器件的方法
公开(公告)号：US08278170B2
公开(公告)日：2012-10-02
申请号：US13165576
申请日：2011-06-21
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： H01L21/336
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

9. 发明申请

US20110180941A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US20110180941A1
公开(公告)日：2011-07-28
申请号：US13012485
申请日：2011-01-24
申请人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang
发明人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang
IPC分类号： H01L23/52 , H01L21/28
CPC分类号： H01L21/768 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.
摘要翻译：提供一种三维半导体器件及其制造方法。该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

10. 发明申请

US20110147801A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US20110147801A1
公开(公告)日：2011-06-23
申请号：US12953748
申请日：2010-11-24
申请人： Jae-Joo SHIM , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Woojin Cho
发明人： Jae-Joo SHIM , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Woojin Cho
IPC分类号： H01L27/06
CPC分类号： H01L23/3157 , H01L21/76816 , H01L23/291 , H01L23/528 , H01L27/11519 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
摘要翻译：提供一种三维半导体器件及其制造方法。三维半导体器件可以包括用于提供间隙区域的模具结构和包括布置在间隙区域中的多个互连图案的互连结构。模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

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