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1. 发明申请

US20090108337A1 Method of and circuit for protecting a transistor formed on a die 有权
标题翻译：用于保护形成在管芯上的晶体管的方法和电路
公开(公告)号：US20090108337A1
公开(公告)日：2009-04-30
申请号：US11977810
申请日：2007-10-26
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/0251
摘要： A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.
摘要翻译：公开了一种保护形成在集成电路的管芯上的晶体管的方法。该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

2. 发明授权

US07772093B2 Method of and circuit for protecting a transistor formed on a die 有权
标题翻译：用于保护形成在管芯上的晶体管的方法和电路
公开(公告)号：US07772093B2
公开(公告)日：2010-08-10
申请号：US11977810
申请日：2007-10-26
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
IPC分类号： H01L21/326 , H01L21/479
CPC分类号： H01L27/0251
摘要： A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.
摘要翻译：公开了一种保护形成在集成电路的管芯上的晶体管的方法。该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

3. 发明授权

US07956385B1 Circuit for protecting a transistor during the manufacture of an integrated circuit device 有权
标题翻译：用于在制造集成电路器件期间保护晶体管的电路
公开(公告)号：US07956385B1
公开(公告)日：2011-06-07
申请号：US12847957
申请日：2010-07-30
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak K. Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak K. Nayak , Daniel Gitlin
IPC分类号： H01L23/525
CPC分类号： H01L27/0251
摘要： A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.
摘要翻译：公开了一种用于在制造集成电路器件期间保护晶体管的电路。该电路包括晶体管，其晶体管具有形成在集成电路器件的管芯中的有源区上的栅极; 形成在集成电路器件的管芯中的保护元件; 以及耦合在所述晶体管的栅极和所述保护元件之间的可编程互连，所述可编程互连使得所述保护元件能够与所述晶体管分离。

4. 发明授权

US07936006B1 Semiconductor device with backfilled isolation 有权
标题翻译：具有回填隔离的半导体器件
公开(公告)号：US07936006B1
公开(公告)日：2011-05-03
申请号：US11244566
申请日：2005-10-06
申请人： Yuhao Luo , Deepak Kumar Nayak , Daniel Gitlin
发明人： Yuhao Luo , Deepak Kumar Nayak , Daniel Gitlin
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1207 , H01L29/0653 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/66772
摘要： An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.
摘要翻译： MOS器件具有在器件的有源部分下方的嵌入式介质结构，例如源延伸或漏极延伸。在替代实施例中，嵌入式介质结构位于MOS器件的沟道区域以及源极和漏极延伸部分之下。

5. 发明授权

US06268639B1 Electrostatic-discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US06268639B1
公开(公告)日：2001-07-31
申请号：US09248547
申请日：1999-02-11
申请人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
发明人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
IPC分类号： H01L218222
CPC分类号： H01L27/0251 , Y10S438/983
摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.
摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。齐纳二极管包括阳极和阴极扩散。阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。阳极扩散通过阴极扩散向下延伸到半导体衬底中。阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

6. 发明授权

US06645802B1 Method of forming a zener diode 有权
标题翻译：形成齐纳二极管的方法
公开(公告)号：US06645802B1
公开(公告)日：2003-11-11
申请号：US09877690
申请日：2001-06-08
申请人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
发明人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
IPC分类号： H01L218234
CPC分类号： H01L27/0251 , Y10S438/983
摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.
摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。齐纳二极管包括阳极和阴极扩散。阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。阳极扩散通过阴极扩散向下延伸到半导体衬底中。阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

7. 发明申请

US20110267103A1 METHOD AND APPARATUS FOR SAVING POWER IN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中节省电力的方法和装置
公开(公告)号：US20110267103A1
公开(公告)日：2011-11-03
申请号：US13127473
申请日：2009-01-07
申请人： Daniel Gitlin , Martin Voogel , Jason Redgrave , Matt Crowley
发明人： Daniel Gitlin , Martin Voogel , Jason Redgrave , Matt Crowley
IPC分类号： H03K19/177
CPC分类号： H03K19/0008 , H03K19/017509 , H03K19/17704 , H03K19/17784
摘要： Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.
摘要翻译：一些实施例提供集成电路（'IC'），其包括以第一电压工作的至少第一和第二电路。 IC包括在第一和第二电路之间的直接连接，其包括用于以低于第一电压的第二电压将信号从第一电路传输到第二电路的第三电路。第一和第二电路中的至少一个是用于可配置地执行操作的可配置电路。

8. 发明授权

US07839693B1 Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer 有权
标题翻译：制造具有横向多层间编程层的CMOS兼容非易失性存储单元的方法
公开(公告)号：US07839693B1
公开(公告)日：2010-11-23
申请号：US12683585
申请日：2010-01-07
申请人： Sunhom Paak , Boon Y. Ang , Hsung J. Im , Daniel Gitlin
发明人： Sunhom Paak , Boon Y. Ang , Hsung J. Im , Daniel Gitlin
IPC分类号： G11C16/06
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/66833
摘要： An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.
摘要翻译：使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。在多晶硅栅极上生长热氧化物以提供隔离层。氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

9. 发明授权

US06621325B2 Structures and methods for selectively applying a well bias to portions of a programmable device 有权
标题翻译：用于选择性地将井偏压施加到可编程设备的部分的结构和方法
公开(公告)号：US06621325B2
公开(公告)日：2003-09-16
申请号：US09956203
申请日：2001-09-18
申请人： Michael J. Hart , Steven P. Young , Daniel Gitlin , Hua Shen , Stephen M. Trimberger
发明人： Michael J. Hart , Steven P. Young , Daniel Gitlin , Hua Shen , Stephen M. Trimberger
IPC分类号： H03K301
CPC分类号： H03K19/17792 , G06F17/5054 , H01L27/0928 , H01L27/11807
摘要： Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.
摘要翻译：用于选择性地将阱偏压施加到PLD的那些需要或期望的偏置的那些部分的结构和方法，例如在用户设计中的关键路径上的晶体管施加正的阱偏置。用于集成电路的衬底包括多个阱，每个阱可以以相同或不同的阱偏置电压独立地且可编程地偏置。在一个实施例中，FPGA实现软件自动地确定关键路径并且生成配置比特流，其使得能够仅对参与关键路径的晶体管施加正阱偏置，或仅对包含那些晶体管的可编程逻辑元件（例如，CLB或查找表）进行偏置。在另一个实施例中，选择性地施加负阱偏置以减少泄漏电流。

10. 发明授权

US5880620A Pass gate circuit with body bias control 失效
标题翻译：通过门电路与体偏置控制
公开(公告)号：US5880620A
公开(公告)日：1999-03-09
申请号：US840582
申请日：1997-04-22
申请人： Daniel Gitlin , Sheau-Suey Li , Martin L. Voogel , Tiemin Zhao
发明人： Daniel Gitlin , Sheau-Suey Li , Martin L. Voogel , Tiemin Zhao
IPC分类号： G11C5/14 , H03K17/06 , H03K3/01
CPC分类号： G11C5/146 , H03K17/063 , H03K2217/0018
摘要： A pass gate circuit includes a pass transistor and a body bias control circuit for biasing the body of the pass transistor to reduce body effect. The body bias control circuit includes one or more control transistors arranged to selectively connect the substrate (body) of the pass transistor to the drain or gate of the pass transistor when predetermined voltages are applied to the drain and gate of the pass transistor. As a result, the pass transistor exhibits a reduced body effect in the on-state. In one embodiment, the body bias control circuit includes a first control transistor having a drain and gate connected to the gate of the pass transistor, a gate connected to the drain of the pass transistor, and a source. The body bias control circuit also includes a second control transistor having a drain connected to the source of the first control transistor, a source connected to a body of the pass transistor, and a gate connected to the drain of the pass transistor. The bodies of the pass transistor, first control transistor and second control transistor are electrically interconnected. With this arrangement, the body of the pass transistor is biased "high" by the gate of the pass transistor only when both the gate and drain of the pass transistor are at a high voltage level.
摘要翻译：通路电路包括通过晶体管和体偏置控制电路，用于偏置通过晶体管的主体以减小体效应。体偏置控制电路包括一个或多个控制晶体管，其布置成当预定电压施加到传输晶体管的漏极和栅极时，选择性地将传输晶体管的衬底（主体）连接到传输晶体管的漏极或栅极。结果，通过晶体管在导通状态下表现出减小的体效应。在一个实施例中，体偏置控制电路包括第一控制晶体管，其具有连接到传输晶体管的栅极的漏极和栅极，连接到传输晶体管的漏极的栅极和源极。体偏置控制电路还包括第二控制晶体管，其具有连接到第一控制晶体管的源极的漏极，连接到传输晶体管的主体的源极和连接到通过晶体管的漏极的栅极。传输晶体管，第一控制晶体管和第二控制晶体管的主体电互连。通过这种布置，只有当传输晶体管的栅极和漏极都处于高电压电平时，传输晶体管的主体被传输晶体管的栅极偏置“高”。

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