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1. 发明授权

US08828224B2 Device for purifying oily wastewater 有权
标题翻译：净化油污水的设备
公开(公告)号：US08828224B2
公开(公告)日：2014-09-09
申请号：US13144865
申请日：2010-06-21
申请人： Xuewen Jiang , Yukai Zhang , Yangshan Wu
发明人： Xuewen Jiang , Yukai Zhang , Yangshan Wu
IPC分类号： C02F1/38 , C02F1/40 , C02F1/52 , B01D21/01 , B01D21/26 , B01D21/24
CPC分类号： C02F1/001 , B01D21/0012 , B01D21/0045 , B01D21/0084 , B01D21/01 , B01D21/08 , B01D21/2411 , B01D21/245 , B01D21/2483 , B01D21/2494 , C02F1/24 , C02F1/40 , C02F1/52 , C02F2103/10 , C02F2103/365 , C02F2301/026
摘要： There is disclosed a device for purifying oily wastewater, including a vertical tank of an atmospheric pressure, inside which a central coagulation reaction tube, a reverse cone-shaped cyclone flocculation stage, a suspended sludge filtering zone and a purified water commutation stage of inclined plates are included from bottom to top sequentially, oily wastewater is sequentially subjected to a coagulation reaction, suspended sludge filtering and a purified water commutation process and then discharged, a sludge collecting groove collects and guides the suspended sludge to a sludge concentrating zone for further sedimentation and concentration processes and then discharges it to external to the tank, in this way, the purification reaction, flocculation and fine filtration of wastewater and the sludge concentration process are integrated within the same wastewater purifying device. Thus, the device is equivalent to the existing wastewater pretreatment system plus a fine filtration system.
摘要翻译：公开了一种用于净化含油废水的装置，包括一个大气压力的立式罐，其中中央凝结反应管，反锥形旋风絮凝段，悬浮污泥过滤区和倾斜板的纯化水换热段从底部到顶部依次包括油性废水依次进行凝结反应，悬浮污泥过滤和纯化水换向，然后排出，污泥收集槽收集并引导悬浮污泥进入污泥浓缩区进行进一步沉淀，浓缩过程，然后将其排放到罐外，以此方式将废水的净化反应，絮凝和精细过滤和污泥浓缩过程集成在同一废水净化装置内。因此，该装置相当于现有的废水预处理系统和精细过滤系统。

2. 发明申请

US20120241904A1 SYMMETRICAL CENTER TAP INDUCTOR STRUCTURE 有权
标题翻译：对称中心TAP电感结构
公开(公告)号：US20120241904A1
公开(公告)日：2012-09-27
申请号：US13052293
申请日：2011-03-21
申请人： Zhaoyin D. Wu , Xuewen Jiang , Parag Upadhyaya
发明人： Zhaoyin D. Wu , Xuewen Jiang , Parag Upadhyaya
IPC分类号： H01L27/10
CPC分类号： H01L27/08
摘要： An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.
摘要翻译：在半导体集成电路（IC）中实现的电感器结构可以包括导体材料的线圈，其包括位于线圈长度的中点处的中心端子。线圈可相对于将中心线平分的中心线对称。线圈可以包括第一差分端子和第二差分端子，每个端子位于线圈的端部并且与中心端子相对。电感器结构可以包括围绕线圈的隔离环。在一些情况下，电感器结构可以包括定位在中心线上的导电材料的返回线。

3. 发明授权

US06924761B2 Differential digital-to-analog converter 失效
标题翻译：差分数模转换器
公开(公告)号：US06924761B2
公开(公告)日：2005-08-02
申请号：US10601038
申请日：2003-06-19
申请人： Xuewen Jiang , Bobby B. Nikjou , Waleed Khalil , Syed R. Naqvi
发明人： Xuewen Jiang , Bobby B. Nikjou , Waleed Khalil , Syed R. Naqvi
IPC分类号： H03M1/06 , H03M1/68 , H03M1/76 , H03M1/78
CPC分类号： H03M1/0682 , H03M1/687 , H03M1/765 , H03M1/785
摘要： Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.
摘要翻译：简而言之，根据本发明的一个实施例，在收发器的发射机路径中使用的差分数模转换器利用差分R2R架构。这种差分数模转换器可以用于具有较高面积效率的更高速度，更低功率和更高分辨率的应用中，例如在WCDMA应用中。

4. 发明授权

US08614599B1 Method and apparatus for powering down a dual supply current source 有权
标题翻译：关闭双电源电源的方法和设备
公开(公告)号：US08614599B1
公开(公告)日：2013-12-24
申请号：US12963154
申请日：2010-12-08
申请人： Adebabay M. Bekele , Aman Sewani , Xuewen Jiang
发明人： Adebabay M. Bekele , Aman Sewani , Xuewen Jiang
IPC分类号： H03K17/687 , G06F1/32 , G05F1/46
CPC分类号： G06F1/26 , G06F1/32 , H03K2217/0054 , Y10T307/696 , Y10T307/724
摘要： One embodiment of an integrated circuit includes a local circuit block, a first power supply for supplying power to a first terminal of the local circuit block, a second power supply for supplying power to a second terminal of the local circuit block, a first transmission gate coupled between the second terminal of the local circuit block and a current path from the second power supply, and a second transmission gate coupled between the current path from the second power supply and a gate of a p-type metal-oxide-semiconductor (PMOS) transistor in the first transmission gate, the second transmission gate including a single transistor.
摘要翻译：集成电路的一个实施例包括本地电路块，用于向本地电路块的第一端子供电的第一电源，用于向本地电路块的第二端子供电的第二电源，第一传输门耦合在本地电路块的第二端子和来自第二电源的电流路径之间，以及耦合在来自第二电源的电流路径和p型金属氧化物半导体（PMOS）的栅极之间的第二传输栅极）晶体管，第二传输门包括单个晶体管。

5. 发明授权

US08218712B1 Method and apparatus for dividing clock frequencies 有权
标题翻译：分频时钟频率的方法和装置
公开(公告)号：US08218712B1
公开(公告)日：2012-07-10
申请号：US12796414
申请日：2010-06-08
申请人： Xuewen Jiang , Adebabay M. Bekele
发明人： Xuewen Jiang , Adebabay M. Bekele
IPC分类号： H03K23/00
CPC分类号： H03K23/546
摘要： A method and apparatus for dividing clock frequencies are disclosed. For example, a circuit according to one embodiment of includes a high-speed divider and a plurality of programmable dividers cascading with the high-speed divider, wherein the plurality of programmable dividers are of a lower speed than the high-speed divider.
摘要翻译：公开了一种用于分频时钟频率的方法和装置。例如，根据一个实施例的电路包括高速分配器和与高速分压器级联的多个可编程分频器，其中多个可编程分频器的速度比高速分频器低。

6. 发明授权

US07928788B2 Double-balanced sinusoidal mixing phase interpolator circuit and method 有权
标题翻译：双平衡正弦混合相位插值电路及方法
公开(公告)号：US07928788B2
公开(公告)日：2011-04-19
申请号：US12183563
申请日：2008-07-31
申请人： Xuewen Jiang
发明人： Xuewen Jiang
IPC分类号： H03H11/16
CPC分类号： H03B28/00
摘要： A double-balanced sinusoidal mixing phase interpolator circuit comprises: a double-balanced gain stage having a first input for receiving a first phasor clock, a second input for receiving a second phasor clock, and a phase interpolator (PI) output, wherein the double-balance gain stage includes (i) a first gain stage having a positive input side and a negative input side for the first phasor clock and (ii) a second gain stage having a positive input side and a negative input side for the second phasor clock; and a sinusoidal digital-to-analog (DAC) stage coupled to the double-balanced gain stage and configured to implement sinusoidal weighting of positive and negative sides of differential DAC current for the first phasor clock and positive and negative sides of differential DAC current for the second phasor clock, wherein the sinusoidal weighting provides uniformly spaced phase steps in the phase interpolator (PI) output.
摘要翻译：双平衡正弦混合相位内插器电路包括：双平衡增益级，具有用于接收第一相量时钟的第一输入端，用于接收第二相量时钟的第二输入端和相位内插器（PI）输出端，其中双平衡增益级包括（i）具有用于第一相量时钟的正输入侧和负输入侧的第一增益级和（ii）具有用于第二相量时钟的正输入侧和负输入侧的第二增益级 ; 以及耦合到双平衡增益级的正弦数字模拟（DAC）级，并且被配置为对于第一相量时钟和差分DAC电流的正和负侧实现差分DAC电流的正侧和负侧的正弦加权第二相量时钟，其中正弦加权在相位插值器（PI）输出中提供均匀间隔的相位步长。

7. 发明授权

US08941974B2 Interdigitated capacitor having digits of varying width 有权
标题翻译：具有不同宽度的数字的交错电容器
公开(公告)号：US08941974B2
公开(公告)日：2015-01-27
申请号：US13229207
申请日：2011-09-09
申请人： Zhaoyin D. Wu , Parag Upadhyaya , Xuewen Jiang
发明人： Zhaoyin D. Wu , Parag Upadhyaya , Xuewen Jiang
IPC分类号： H01G4/008 , H01G4/228 , H01G4/005 , H01L49/02
CPC分类号： H01L28/86 , Y10T29/43
摘要： An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits.
摘要翻译：公开了具有变化宽度的数字的交错电容器。电容器的一个实施例包括以与第一多个导电数字互锁的方式定位的第一多个导电数字和第二多个导电数字，使得形成叉指结构。第一组多个导电数字和第二多个导电数字共同形成一组数字，其中数字组中第一个数字的宽度相对于该组数字中的第二个数字是不均匀的。

8. 发明申请

US20130063861A1 INTERDIGITATED CAPACITOR HAVING DIGITS OF VARYING WIDTH 有权
标题翻译：具有变化幅度的数字电容器
公开(公告)号：US20130063861A1
公开(公告)日：2013-03-14
申请号：US13229207
申请日：2011-09-09
申请人： Zhaoyin D. Wu , Parag Upadhyaya , Xuewen Jiang
发明人： Zhaoyin D. Wu , Parag Upadhyaya , Xuewen Jiang
IPC分类号： H01G4/008 , H01G7/00 , H01G4/005
CPC分类号： H01L28/86 , Y10T29/43
摘要： An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits.
摘要翻译：公开了具有变化宽度的数字的交错电容器。电容器的一个实施例包括以与第一多个导电数字互锁的方式定位的第一多个导电数字和第二多个导电数字，使得形成叉指结构。第一组多个导电数字和第二多个导电数字共同形成一组数字，其中数字组中第一个数字的宽度相对于该组数字中的第二个数字是不均匀的。

9. 发明授权

US08134418B2 Varactor circuit and voltage-controlled oscillation 有权
标题翻译：变容二极管电路和电压控制振荡
公开(公告)号：US08134418B2
公开(公告)日：2012-03-13
申请号：US12759658
申请日：2010-04-13
申请人： Xuewen Jiang
发明人： Xuewen Jiang
IPC分类号： H03C3/20 , H03B5/12
CPC分类号： H03J3/20
摘要： A varactor circuit and voltage-controlled oscillation are described. The varactor circuit includes a first varactor, a second varactor, a third varactor, and a fourth varactor. A first source-drain node of the first varactor and a second source-drain node of the second varactor are coupled to a first input node. A first gate node for the first varactor is coupled to a first output node. A second gate node for the second varactor is coupled to a second output node. A third gate node for the third varactor and a fourth gate node for the fourth varactor are coupled to a second input node. A third source-drain node of the third varactor is coupled to the first output node. A fourth source-drain node of the fourth varactor is coupled to the second output node. In other embodiments, varactor circuits block and re-center VCO output CML.
摘要翻译：描述了变容二极管电路和压控振荡。变容二极管电路包括第一变容二极管，第二变容二极管，第三变容二极管和第四变容二极管。第一变容二极管的第一源极 - 漏极节点和第二变容二极管的第二源极 - 漏极节点耦合到第一输入节点。用于第一变容二极管的第一门节点耦合到第一输出节点。用于第二变容二极管的第二门节点耦合到第二输出节点。用于第三变容二极管的第三栅极节点和用于第四变容二极管的第四栅极节点耦合到第二输入节点。第三变容二极管的第三源极 - 漏极节点耦合到第一输出节点。第四变容二极管的第四源极 - 漏极节点耦合到第二输出节点。在其他实施例中，变容二极管电路阻塞并重新调谐VCO输出CML。

10. 发明授权

US07764091B2 Square to pseudo-sinusoidal clock conversion circuit and method 有权
标题翻译：正方形正弦时钟转换电路及方法
公开(公告)号：US07764091B2
公开(公告)日：2010-07-27
申请号：US12183550
申请日：2008-07-31
申请人： Xuewen Jiang
发明人： Xuewen Jiang
IPC分类号： H03B28/00
CPC分类号： H03B28/00
摘要： A square wave to pseudo-sinusoidal clock conversion circuit comprises first and second stages. The first stage includes a cross-coupled differential pairs input gain stage having positive and negative input sides. Responsive to a differential square wave clock input, the first stage provides a first pass balanced differential clock with pull-up and pull-down symmetry. The second stage comprises positive and negative output side push-pull with low pass filter circuits, wherein the positive and negative output side push-pull with low pass filter circuits are responsive to the first pass balanced differential clock from the first stage for producing an output pseudo-sinusoidal clock that comprises a nearly sinusoidal output with slew rate controlled and clock waveform pull-up and pull-down symmetry for each of a respective one of the positive and negative output sides.
摘要翻译：方波到伪正弦时钟转换电路包括第一和第二级。第一级包括具有正和负输入侧的交叉耦合差分对输入增益级。响应于差分方波时钟输入，第一级提供具有上拉和下拉对称性的第一通路平衡差分时钟。第二级包括具有低通滤波器电路的正和负输出侧推挽，其中具有低通滤波器电路的正和负输出侧推挽响应于来自第一级的第一通过平衡差分时钟，用于产生输出伪正弦时钟，其包括具有压摆率控制的近似正弦输出，并且正和负输出侧中的相应一个的时钟波形上拉和下拉对称。

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