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    • 4. 发明授权
    • Method of making edge-aligned implants and electrodes therefor
    • 制造边缘对准植入物和电极的方法
    • US4613402A
    • 1986-09-23
    • US750204
    • 1985-07-01
    • David L. LoseeJames P. Lavine
    • David L. LoseeJames P. Lavine
    • H01L29/762H01L21/339H01L21/8234H01L27/14H01L27/148H01L29/76H01L29/772H01L21/306B44C1/22C03C15/00C23F1/02
    • H01L29/66954H01L21/823406
    • There is disclosed a process particularly suited for making CCD's. The process comprises the steps of(a) depositing a layer of conductive material above a semiconductor substrate;(b) forming a patterned mask above the conductive layer, the pattern exposing spaced-apart strip portions of the conductive layer;(c) ion-implanting dopant strips into the substrate through the conductive layer strip portions exposed by the patterned mask;(d) removing a portion of the mask but retaining the rest so as to expose the conductive layer over first portions of the substrate that contain an implanted dopant strip and over portions of the substrate adjacent to the first portions;(e) forming on the conductive layer between the retained mask portions, and above the implanted dopant strips, strips of a material resistant to an etchant for the conductive material;(f) removing the retained mask portions; and(g) etching away the conductive layer where the latter is not covered with the etchant-resistant material so as to leave conductive strips overlying the implanted strips.
    • 公开了一种特别适用于制造CCD的工艺。 该方法包括以下步骤:(a)在半导体衬底上沉积导电材料层; (b)在所述导电层上方形成图案化掩模,所述图案暴露所述导电层的间隔开的条带部分; (c)通过由图案化掩模暴露的导电层条带部分将掺杂剂条带离子注入到衬底中; (d)去除所述掩模的一部分,但保留其余部分,以使所述导电层暴露于所述衬底的第一部分上,所述第一部分包含注入的掺杂剂条和所述衬底的与所述第一部分相邻的部分; (e)在所述保护的掩模部分之间和所述注入的掺杂剂条带之上的所述导电层上形成耐导电材料的蚀刻剂的材料条; (f)去除保留的掩模部分; 并且(g)蚀刻掉导电层,其中后者不被耐蚀刻材料覆盖,以便留下覆盖在植入条上的导电条。
    • 8. 发明授权
    • Image sensor with improved output region for superior charge transfer
characteristics
    • 图像传感器具有改进的输出区域,具有出色的电荷转移特性
    • US5514886A
    • 1996-05-07
    • US374280
    • 1995-01-18
    • Eric G. StevensJames P. Lavine
    • Eric G. StevensJames P. Lavine
    • H01L21/339H01L27/148H01L29/762H01L29/768H04N5/372H04N5/378
    • H01L29/76816H01L27/14831
    • The new CCD output region provides a method of reducing the width of a wide CCD at its output to maintain a high sensitivity output node without sacrificing charge-transfer efficiency. A barrier region is shaped so the "channel width" of the CCD increases towards the input edge of the output gate. The barrier region, therefore, decreases in width towards the output end of the final CCD phase of a multi-phase device. Also, the channel width under the output gate decreases towards its output end in the direction of charge transfer towards the floating diffusion, or detection node. Since the "shaped" portion of the barrier region under the last CCD phase can be formed by the same process steps as the regular-shaped barrier regions, it is possible to form this structure without the requirement for additional masking and implant steps. The advantages of this structure over the prior art are improved charge-transfer characteristics without requiring additional process steps.
    • 新的CCD输出区域提供了在其输出端减小宽CCD的宽度以维持高灵敏度输出节点而不牺牲电荷传输效率的方法。 阻挡区域的形状使得CCD的“通道宽度”朝向输出门的输入边缘增加。 因此,阻挡区域的宽度朝向多相设备的最终CCD相的输出端减小。 此外,输出栅极下的沟道宽度朝向浮动扩散或检测节点的电荷转移方向朝向其输出端减小。 由于最后CCD相位下的阻挡区域的“成形”部分可以通过与正常形状的阻挡区域相同的工艺步骤形成,所以可以形成这种结构,而不需要额外的掩模和注入步骤。 与现有技术相比,该结构的优点是改进的电荷转移特性,而不需要额外的工艺步骤。
    • 10. 发明授权
    • Method of making a single electrode level CCD
    • 制造单电极级CCD的方法
    • US5314836A
    • 1994-05-24
    • US945073
    • 1992-09-15
    • James P. Lavine
    • James P. Lavine
    • H01L21/339H01L29/423
    • H01L29/66954H01L29/42396Y10S148/111
    • The disclosure is directed to a method of forming a CCD with two sets of gate electrodes in a single layer of a conductive material. The method comprises forming a channel region in a body of a semiconductor material along a surface thereof and forming a layer of conductive material over and insulated from the surface of the body. A first masking layer is formed on the conductive layer and spaced strips of polycrystalline silicon are formed on the first masking layer. Using a portion of the spaces between the strips as a mask, impurities of a conductivity type opposite that of the channel region are embedded in the channel region to form spaced barrier regions along the channel region. A layer of silicon dioxide is formed over each of the strips and the spaces between the strips are filled with polycrystalline silicon. The portion of the silicon dioxide layer at one end of each of the strips is etched away to expose a portion of the first masking layer. The exposed portions of the first masking layer are etched away to form grooves through the first masking layer to the conductive layer. The portions of the conductive layer at the bottom of the grooves are then etched away to define the conductive layer into closely spaced gate electrodes.
    • 本公开涉及一种在导电材料的单层中形成具有两组栅电极的CCD的方法。 该方法包括在半导体材料的主体中沿着其表面形成沟道区,并且在主体的表面上形成绝缘层和导电材料。 在导电层上形成第一掩模层,并且在第一掩模层上形成间隔开的多晶硅条。 使用条带之间的一部分空间作为掩模,导电类型与沟道区域相反的杂质被嵌入在沟道区域中,以形成沿沟道区域的间隔开的阻挡区域。 在每个条上形成二氧化硅层,并且条之间的空间填充有多晶硅。 每个条带的一端处的二氧化硅层的部分被蚀刻掉以露出第一掩模层的一部分。 蚀刻掉第一掩模层的暴露部分,以形成通过第一掩模层到导电层的凹槽。 然后蚀刻掉在凹槽底部的导电层的部分,以将导电层限定成紧密隔开的栅电极。