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1. 发明授权

US07523230B1 Device and method for maximizing performance on a memory interface with a variable number of channels 失效
标题翻译：用于使具有可变数量的通道的存储器接口上的性能最大化的装置和方法
公开(公告)号：US07523230B1
公开(公告)日：2009-04-21
申请号：US11137314
申请日：2005-05-24
申请人： James M. Dodd , Brian P. Johnson , Jay C. Wells , John B. Halbert
发明人： James M. Dodd , Brian P. Johnson , Jay C. Wells , John B. Halbert
IPC分类号： G06F13/28 , G06F13/00 , G06F13/14 , G06F3/00 , G06F12/00
CPC分类号： G06F13/1668 , G11C7/1027 , G11C7/1066 , G11C7/1072
摘要： The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
摘要翻译：本发明包括一种用于控制在存储器件上执行的读和写操作的数据长度的方法和装置。该方法包括确定可操作地耦合到存储器件的存储器控制器可用的第一数量的通道; 确定填充频道的数量的第二数字代表; 基于第一和第二数字计算突发长度; 并且对存储器控制器进行编程以使用突发长度作为在存储器件上执行的读和写操作的数据长度。

2. 发明授权

US06766385B2 Device and method for maximizing performance on a memory interface with a variable number of channels 有权
标题翻译：用于使具有可变数量的通道的存储器接口上的性能最大化的装置和方法
公开(公告)号：US06766385B2
公开(公告)日：2004-07-20
申请号：US10041679
申请日：2002-01-07
申请人： James M. Dodd , Brian P. Johnson , Jay C. Wells , John B. Halbert
发明人： James M. Dodd , Brian P. Johnson , Jay C. Wells , John B. Halbert
IPC分类号： G06F1328
CPC分类号： G06F13/1668 , G11C7/1027 , G11C7/1066 , G11C7/1072
摘要： The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
摘要翻译：本发明包括一种用于控制在存储器件上执行的读和写操作的数据长度的方法和装置。该方法包括确定可操作地耦合到存储器件的存储器控制器可用的第一数量的通道; 确定填充频道的数量的第二数字代表; 基于第一和第二数字计算突发长度; 并且对存储器控制器进行编程以使用突发长度作为在存储器件上执行的读和写操作的数据长度。

3. 发明授权

US06952745B1 Device and method for maximizing performance on a memory interface with a variable number of channels 有权
标题翻译：用于使具有可变数量的通道的存储器接口上的性能最大化的装置和方法
公开(公告)号：US06952745B1
公开(公告)日：2005-10-04
申请号：US10877387
申请日：2004-06-25
申请人： James M. Dodd , Brian P. Johnson , Jay C. Wells , John B. Halbert
发明人： James M. Dodd , Brian P. Johnson , Jay C. Wells , John B. Halbert
IPC分类号： G06F13/16 , G11C7/10 , G06F13/28 , G06F3/00 , G06F12/00 , G06F13/00 , G06F13/14
CPC分类号： G06F13/1668 , G11C7/1027 , G11C7/1066 , G11C7/1072
摘要： The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
摘要翻译：本发明包括一种用于控制在存储器件上执行的读和写操作的数据长度的方法和装置。该方法包括确定可操作地耦合到存储器件的存储器控制器可用的第一数量的通道; 确定填充频道的数量的第二数字代表; 基于第一和第二数字计算突发长度; 并且对存储器控制器进行编程以使用突发长度作为在存储器件上执行的读和写操作的数据长度。

4. 发明授权

US06742098B1 Dual-port buffer-to-memory interface 有权
标题翻译：双端口缓冲存储器接口
公开(公告)号：US06742098B1
公开(公告)日：2004-05-25
申请号：US09678751
申请日：2000-10-03
申请人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G06F1200
CPC分类号： G06F13/4256
摘要： Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.
摘要翻译：公开了使用新的存储器模块结构的存储器系统的方法和装置。在一个实施例中，存储器模块具有两个等级的存储器件，每个等级连接到两个64位宽数据寄存器中对应的一个。数据寄存器连接到120：64多路复用器/解复用器的两个64位宽端口，64位宽数据缓冲器连接到多路复用器/解复用器的相对端口。控制器同步数据寄存器，多路复用器/解复用器和数据缓冲器的操作。在操作环境中，数据缓冲器连接到存储器总线。当执行数据访问时，在单个数据访问期间，两者都与其对应的数据寄存器交换数据信令。在缓冲器中，存储器总线数据传输发生在两个连续的时钟周期中，每个等级都有一个周期。这允许存储器总线传输速率对于相同的存储器总线宽度和存储器件速度来说是双倍的。

5. 发明授权

US06449213B1 Memory interface having source-synchronous command/address signaling 有权
标题翻译：具有源同步命令/地址信令的存储器接口
公开(公告)号：US06449213B1
公开(公告)日：2002-09-10
申请号：US09664192
申请日：2000-09-18
申请人： James M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella
发明人： James M. Dodd , Michael W. Williams , John B. Halbert , Randy M. Bonella
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C5/063 , G11C7/1087 , G11C8/00 , G11C8/06
摘要： A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that samples address/command information responsive to an address/command strobe signal and then passes the address/command information to a memory device on the module. A retiming circuit may be used to control the timing of read-return data from a memory device on the module.
摘要翻译：存储器接口方案通过利用源同步信令将地址/命令信息发送到存储器件来减少传播延迟。根据本发明的存储器模块可以包括地址/命令缓冲器，其响应于地址/命令选通信号对地址/命令信息进行采样，然后将地址/命令信息传递到模块上的存储器件。可以使用重新定时电路来控制来自模块上的存储器件的读取数据的定时。

6. 发明授权

US06493250B2 Multi-tier point-to-point buffered memory interface 有权
标题翻译：多层点对点缓冲存储器接口
公开(公告)号：US06493250B2
公开(公告)日：2002-12-10
申请号：US09753024
申请日：2000-12-28
申请人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella
发明人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella
IPC分类号： G11C506
CPC分类号： G06F13/4256
摘要： Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.
摘要翻译：公开了使用分支点对点存储器总线架构的存储器系统的方法和装置。在一个实施例中，主存储器控制器维护与一个存储器模块的点对点总线连接，并且该存储器模块与第二模块维护单独的点到点总线连接。存储器控制器和第二存储器模块之间的数据通过第一存储器模块上的缓冲电路。对于从存储器控制器接收到的数据，缓冲电路还将该数据上传到模块总线段到第一组存储器件。该存储器组存储有第二组存储器件的第二模块总线段。在缓冲电路和第二组存储器件之间的数据通过在第一存储器件组上通过一个通过电路。以这种方式，即使当存储器模块包含多于一组的存储器设备时，也可以维持点对点存储器总线体系结构。

7. 发明授权

US07024518B2 Dual-port buffer-to-memory interface 失效
公开(公告)号：US07024518B2
公开(公告)日：2006-04-04
申请号：US10100312
申请日：2002-03-13
申请人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella , Thomas J. Holman
发明人： John B. Halbert , James M. Dodd , Chung Lam , Randy M. Bonella , Thomas J. Holman
IPC分类号： G06F12/00
CPC分类号： G11C7/1051 , G06F13/1689 , G06F13/1694 , G11C5/00 , G11C5/025 , G11C7/1012 , G11C7/1066 , G11C2207/108
摘要： Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 128:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer.In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

8. 发明授权

US09396784B2 Reduction of power consumption in memory devices during refresh modes 有权
标题翻译：在刷新模式下降低存储设备的功耗
公开(公告)号：US09396784B2
公开(公告)日：2016-07-19
申请号：US13997959
申请日：2012-03-27
申请人： Christopher E. Cox , Kuljit S. Bains , John B. Halbert
发明人： Christopher E. Cox , Kuljit S. Bains , John B. Halbert
IPC分类号： G11C16/24 , G11C11/406 , G11C11/4074
CPC分类号： G11C11/40615 , G11C7/00 , G11C7/08 , G11C11/40611 , G11C11/4074 , G11C11/409 , G11C11/4096 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C2211/4065 , G11C2211/4068
摘要： Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.
摘要翻译：设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平至少一个寄存器源。

9. 发明申请

US20160163376A1 APPARATUS, METHOD AND SYSTEM FOR PERFORMING SUCCESSIVE WRITES TO A BANK OF A DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：用于对动态随机访问存储器的银行执行后续写入的装置，方法和系统
公开(公告)号：US20160163376A1
公开(公告)日：2016-06-09
申请号：US14940073
申请日：2015-11-12
申请人： Kuljit S. Bains , John B. Halbert
发明人： Kuljit S. Bains , John B. Halbert
IPC分类号： G11C11/4093 , G11C11/4096 , G11C29/44 , G11C11/4076
CPC分类号： G11C11/4093 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C29/52 , G11C2029/0411
摘要： Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.
摘要翻译：提供对存储设备的写入访问的技术和机制。在一个实施例中，存储器控制器向包括多个存储体的存储器件发送命令。存储器控制器进一步发送一个信号，该信号指定每个命令包括背靠背写入命令以访问相同的存储体。响应于该信号，存储器件缓冲第一写入命令的第一数据，其中至少缓冲第一数据直到存储器件接收第二写入命令的第二数据。针对第一数据和第二数据的组合计算误差校正信息，并将该组合写入存储体。在另一个实施例中，基于来自存储器控制器的信号，代替第一数据的读 - 修改 - 写处理，执行第一数据的缓冲和第一数据与第二数据的组合。

10. 发明授权

US09030903B2 Method, apparatus and system for providing a memory refresh 有权
标题翻译：用于提供存储器刷新的方法，装置和系统
公开(公告)号：US09030903B2
公开(公告)日：2015-05-12
申请号：US13625741
申请日：2012-09-24
申请人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
IPC分类号： G11C11/406 , G11C16/00 , G06F13/16
CPC分类号： G11C16/00 , G06F13/1636 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.
摘要翻译：一个内存控制器，用于实现行锤事件潜在的受害者行的目标刷新。在一个实施例中，存储器控制器接收指示存储器设备的特定行正经历重复访问，这威胁到与特定行物理相邻的一个或多个受害者行中的数据的完整性。存储器控制器在没有指定存储器件的物理相邻行之间的偏移的地址映射信息的情况下访问默认偏移信息。在另一个实施例中，存储器控制器基于默认偏移信息来确定潜在的受害者行的地址。响应于所接收到的行锤事件的指示，存储器控制器向确定的多个地址中的每一个发送相应的命令给存储器设备，其中命令用于存储设备执行目标刷新潜在的受害者行。

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