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1. 发明申请

US20160093344A1 METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND SIGNALING 有权
标题翻译：方法，装置和系统来管理隐式预充电指令信号
公开(公告)号：US20160093344A1
公开(公告)日：2016-03-31
申请号：US14498509
申请日：2014-09-26
申请人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
发明人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G06F13/1668 , G06F13/1689 , G06F21/79 , G11C7/1045 , G11C7/1048 , G11C7/1063 , G11C7/109 , G11C11/4076 , G11C11/4093 , G11C11/4094 , Y02D10/14
摘要： Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.
摘要翻译：用于在存储器控制器和存储器件之间交换信息的技术和机制。在一个实施例中，存储器控制器接收指示存储器设备访问该存储器设备的临时统一激活命令的阈值数量的信息。由信息指示的阈值数小于待处理的合并激活命令的理论最大数量，基于存储器件的定时参数定义的理论最大数量。在另一个实施例中，存储器控制器基于指示阈值数量的信息来限制合并的激活命令到存储器设备的通信。

2. 发明授权

US08938573B2 Row hammer condition monitoring 有权
标题翻译：行锤状态监测
公开(公告)号：US08938573B2
公开(公告)日：2015-01-20
申请号：US13539417
申请日：2012-06-30
申请人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
发明人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
IPC分类号： G06F12/06 , G11C11/406 , G06F11/30
CPC分类号： G06F11/3037 , G06F11/004 , G06F11/3471 , G06F2201/81 , G06F2201/88 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.
摘要翻译：系统监视对特定行存储器的数据访问，以确定是否存在行锤条件。该系统可以监视所访问的存储行，以确定对任何行的访问次数是否超过与物理上与高访问行相邻的存储体上的数据损坏风险相关联的阈值。基于监视，存储器控制器可以确定对行的访问次数是否超过阈值，并且指示访问计数达到阈值的行的地址信息。

3. 发明申请

US20140089576A1 METHOD, APPARATUS AND SYSTEM FOR PROVIDING A MEMORY REFRESH 有权
标题翻译：方法，提供记忆刷新的装置和系统
公开(公告)号：US20140089576A1
公开(公告)日：2014-03-27
申请号：US13625741
申请日：2012-09-24
申请人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
IPC分类号： G06F12/00
CPC分类号： G11C16/00 , G06F13/1636 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.
摘要翻译：一个内存控制器，用于实现行锤事件潜在的受害者行的目标刷新。在一个实施例中，存储器控制器接收指示存储器设备的特定行正经历重复访问，这威胁到与特定行物理相邻的一个或多个受害者行中的数据的完整性。存储器控制器在没有指定存储器件的物理相邻行之间的偏移的地址映射信息的情况下访问默认偏移信息。在另一个实施例中，存储器控制器基于默认偏移信息来确定潜在的受害者行的地址。响应于所接收到的行锤事件的指示，存储器控制器向确定的多个地址中的每一个发送相应的命令给存储器设备，其中命令用于存储设备执行目标刷新潜在的受害者行。

4. 发明申请

US20130117641A1 METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：用于存储器件中的错误管理的方法和系统
公开(公告)号：US20130117641A1
公开(公告)日：2013-05-09
申请号：US13619452
申请日：2012-09-14
申请人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
发明人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/1016
摘要： A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.
摘要翻译：一种用于存储器件中的错误管理的方法和系统。在本发明的一个实施例中，存储器设备可以处理命令和寻址奇偶校验错误和循环冗余校验错误。在本发明的一个实施例中，存储器可以通过确定接收到的命令的命令位或地址位是否具有任何奇偶校验错误来检测所接收的命令是否具有任何奇偶校验错误。如果检测到接收到的命令中的奇偶校验错误或循环冗余校验错误，则触发错误处理机制以从错误命令中恢复。

5. 发明申请

US20090327660A1 MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT 有权
标题翻译：通过预付费管理的精细化，存储器增加
公开(公告)号：US20090327660A1
公开(公告)日：2009-12-31
申请号：US12165214
申请日：2008-06-30
申请人： Kuljit S. Bains , John B. Halbert
发明人： Kuljit S. Bains , John B. Halbert
IPC分类号： G06F9/44
CPC分类号： G06F13/161 , Y02D10/14
摘要： Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed.
摘要翻译：描述了用于提高存储器设备中的吞吐量的方法和装置。在一个实施例中，通过预充电管理的细粒度来增加存储器吞吐量。在一个实施例中，可以使用三个单独的预充电定时，例如每个存储体组和/或每个存储器件优化每个存储体。还公开并要求保护其他实施例。

6. 发明授权

US07281079B2 Method and apparatus to counter mismatched burst lengths 有权
标题翻译：用于计算不匹配突发长度的方法和装置
公开(公告)号：US07281079B2
公开(公告)日：2007-10-09
申请号：US10750154
申请日：2003-12-31
申请人： Kuljit S. Bains , John B. Halbert , Randy B. Osborne
发明人： Kuljit S. Bains , John B. Halbert , Randy B. Osborne
IPC分类号： G06F12/00
CPC分类号： G06F13/161
摘要： Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.
摘要翻译：具有存储单元组的存储器单元被组织成共享控制电路的两组存储体，以及数据缓冲器以提供与存储器总线的接口，但它们独立地可操作以足以支持与每个组的无关交易，并且可以用于交错以缩短的突发传输进行读操作，以最大限度地减少内存总线上的死区时间。

7. 发明授权

US09396784B2 Reduction of power consumption in memory devices during refresh modes 有权
标题翻译：在刷新模式下降低存储设备的功耗
公开(公告)号：US09396784B2
公开(公告)日：2016-07-19
申请号：US13997959
申请日：2012-03-27
申请人： Christopher E. Cox , Kuljit S. Bains , John B. Halbert
发明人： Christopher E. Cox , Kuljit S. Bains , John B. Halbert
IPC分类号： G11C16/24 , G11C11/406 , G11C11/4074
CPC分类号： G11C11/40615 , G11C7/00 , G11C7/08 , G11C11/40611 , G11C11/4074 , G11C11/409 , G11C11/4096 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C2211/4065 , G11C2211/4068
摘要： Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.
摘要翻译：设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平至少一个寄存器源。

8. 发明申请

US20160163376A1 APPARATUS, METHOD AND SYSTEM FOR PERFORMING SUCCESSIVE WRITES TO A BANK OF A DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：用于对动态随机访问存储器的银行执行后续写入的装置，方法和系统
公开(公告)号：US20160163376A1
公开(公告)日：2016-06-09
申请号：US14940073
申请日：2015-11-12
申请人： Kuljit S. Bains , John B. Halbert
发明人： Kuljit S. Bains , John B. Halbert
IPC分类号： G11C11/4093 , G11C11/4096 , G11C29/44 , G11C11/4076
CPC分类号： G11C11/4093 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C29/52 , G11C2029/0411
摘要： Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.
摘要翻译：提供对存储设备的写入访问的技术和机制。在一个实施例中，存储器控制器向包括多个存储体的存储器件发送命令。存储器控制器进一步发送一个信号，该信号指定每个命令包括背靠背写入命令以访问相同的存储体。响应于该信号，存储器件缓冲第一写入命令的第一数据，其中至少缓冲第一数据直到存储器件接收第二写入命令的第二数据。针对第一数据和第二数据的组合计算误差校正信息，并将该组合写入存储体。在另一个实施例中，基于来自存储器控制器的信号，代替第一数据的读 - 修改 - 写处理，执行第一数据的缓冲和第一数据与第二数据的组合。

9. 发明授权

US09030903B2 Method, apparatus and system for providing a memory refresh 有权
标题翻译：用于提供存储器刷新的方法，装置和系统
公开(公告)号：US09030903B2
公开(公告)日：2015-05-12
申请号：US13625741
申请日：2012-09-24
申请人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Suneeta Sah , Zvika Greenfield
IPC分类号： G11C11/406 , G11C16/00 , G06F13/16
CPC分类号： G11C16/00 , G06F13/1636 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller to implement targeted refreshes of potential victim rows of a row hammer event. In an embodiment, the memory controller receives an indication that a specific row of a memory device is experiencing repeated accesses which threaten the integrity of data in one or more victim rows physically adjacent to the specific row. The memory controller accesses default offset information in the absence of address map information which specifies an offset between physically adjacent rows of the memory device. In another embodiment, the memory controller determines addresses for potential victim rows based on the default offset information. In response to the received indication of the row hammer event, the memory controller sends for each of the determined plurality of addresses a respective command to the memory device, where the commands are for the memory device to perform targeted refreshes of potential victim rows.
摘要翻译：一个内存控制器，用于实现行锤事件潜在的受害者行的目标刷新。在一个实施例中，存储器控制器接收指示存储器设备的特定行正经历重复访问，这威胁到与特定行物理相邻的一个或多个受害者行中的数据的完整性。存储器控制器在没有指定存储器件的物理相邻行之间的偏移的地址映射信息的情况下访问默认偏移信息。在另一个实施例中，存储器控制器基于默认偏移信息来确定潜在的受害者行的地址。响应于所接收到的行锤事件的指示，存储器控制器向确定的多个地址中的每一个发送相应的命令给存储器设备，其中命令用于存储设备执行目标刷新潜在的受害者行。

10. 发明申请

US20150067437A1 APPARATUS, METHOD AND SYSTEM FOR REPORTING DYNAMIC RANDOM ACCESS MEMORY ERROR INFORMATION 审中-公开
标题翻译：用于报告动态随机存取存储器错误信息的装置，方法和系统
公开(公告)号：US20150067437A1
公开(公告)日：2015-03-05
申请号：US14133288
申请日：2013-12-18
申请人： Kuljit S. Bains , John B. Halbert
发明人： Kuljit S. Bains , John B. Halbert
IPC分类号： H03M13/05
CPC分类号： G06F11/1048
摘要： Techniques and mechanisms for providing state information describing one or more data errors detected locally at a memory device. In an embodiment, the memory device includes a memory core and error detection circuit logic configured to detect for errors of data stored by the memory core. A die of the memory device includes both the memory core and the error detection circuitry. In another embodiment, state information is stored in a mode register of the memory device in response to the error detection logic detecting an occurrence of a data error. The state information is available for access by a memory controller or other agent which is external to the memory device.
摘要翻译：用于提供描述在存储器设备本地检测的一个或多个数据错误的状态信息的技术和机制。在一个实施例中，存储器件包括存储器核心和错误检测电路逻辑，其被配置为检测由存储器核心存储的数据的错误。存储器件的管芯包括存储器核心和错误检测电路。在另一个实施例中，响应于错误检测逻辑检测数据错误的发生，将状态信息存储在存储器件的模式寄存器中。状态信息可用于由存储器设备外部的存储器控制器或其他代理进行访问。

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