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1. 发明授权

US5661055A Method of making nonvolatile memory cell with vertical gate overlap and zero birds' beaks 失效
标题翻译：制造具有垂直门重叠和零鸟喙的非易失性存储单元的方法
公开(公告)号：US5661055A
公开(公告)日：1997-08-26
申请号：US474610
申请日：1995-06-07
申请人： James Juen Hsu , Steven W. Longcor , Jih-Chang Lien
发明人： James Juen Hsu , Steven W. Longcor , Jih-Chang Lien
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.
摘要翻译：诸如闪存EEPROM的存储器件具有零鸟嘴和垂直重叠的门，以便于EEPROM的核心中的高电池密度。在制造期间，在芯上形成一层场氧化物。通过蚀刻通过场氧化物层暴露有源区域，以在活性区域周围形成垂直壁的空腔。在每个空腔内形成隧道氧化物，浮栅，互间电介质和控制栅极，使得浮栅与垂直壁重叠。结果，保持栅极之间的电容耦合，但是电池的水平尺寸减小。类似地，没有鸟的喙有助于核心中更高的细胞密度。

2. 发明授权

US5680345A Nonvolatile memory cell with vertical gate overlap and zero birds beaks 失效
标题翻译：具有垂直门重叠和零鸟喙的非易失性存储单元
公开(公告)号：US5680345A
公开(公告)日：1997-10-21
申请号：US469953
申请日：1995-06-06
申请人： James Juen Hsu , Steven W. Longcor , Jih-Chang Lien
发明人： James Juen Hsu , Steven W. Longcor , Jih-Chang Lien
IPC分类号： H01L21/8247 , H01L21/265 , H01L21/225
CPC分类号： H01L27/11521
摘要： A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.
摘要翻译：诸如闪存EEPROM的存储器件具有零鸟嘴和垂直重叠的门，以便于EEPROM的核心中的高电池密度。在制造期间，在芯上形成一层场氧化物。通过蚀刻通过场氧化物层暴露有源区域，以在活性区域周围形成垂直壁的空腔。在每个空腔内形成隧道氧化物，浮栅，互间电介质和控制栅极，使得浮栅与垂直壁重叠。结果，保持栅极之间的电容耦合，但是电池的水平尺寸减小。类似地，没有鸟的喙有助于核心中更高的细胞密度。

3. 发明授权

US4987465A Electro-static discharge protection device for CMOS integrated circuit inputs 失效
标题翻译：用于CMOS集成电路输入的静电放电保护装置
公开(公告)号：US4987465A
公开(公告)日：1991-01-22
申请号：US266223
申请日：1988-10-28
申请人： Steven W. Longcor , Kuang-Yeh Chang , Jih-Chang Lien , David M. Rogers
发明人： Steven W. Longcor , Kuang-Yeh Chang , Jih-Chang Lien , David M. Rogers
IPC分类号： H01L27/02
CPC分类号： H01L27/0259 , H01L27/0266
摘要： An ESD protection device for CMOS integrated circuit inputs is disclosed. Two clamp components, coupled by a current limiting device, couple the pad to the circuitry of the chip. The device prevents damage to the circuit from an ESD of approximately 8000 or more volts at an input terminal.
摘要翻译：公开了一种用于CMOS集成电路输入的ESD保护装置。通过限流装置耦合的两个钳位部件将焊盘耦合到芯片的电路。该装置防止在输入端子处从约8000或更高电压的ESD损坏电路。

4. 发明申请

US20110204019A1 Method of making a planar electrode 审中-公开
标题翻译：制作平面电极的方法
公开(公告)号：US20110204019A1
公开(公告)日：2011-08-25
申请号：US12927552
申请日：2010-11-15
申请人： Jonathan Bornstein , David Hansen , Steven W. Longcor
发明人： Jonathan Bornstein , David Hansen , Steven W. Longcor
IPC分类号： H05K3/00
摘要： Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
摘要翻译：公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。

5. 发明授权

US07832090B1 Method of making a planar electrode 失效
标题翻译：制作平面电极的方法
公开(公告)号：US07832090B1
公开(公告)日：2010-11-16
申请号：US12660424
申请日：2010-02-25
申请人： Jonathan Bornstein , David Hansen , Steven W. Longcor
发明人： Jonathan Bornstein , David Hansen , Steven W. Longcor
IPC分类号： H01R43/00
CPC分类号： H01L27/24 , H01L21/3212 , H01L21/7684 , H01L21/76849 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
摘要翻译：公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。

6. 发明授权

US07633790B2 Multi-resistive state memory device with conductive oxide electrodes 失效
标题翻译：具有导电氧化物电极的多电阻状态存储器件
公开(公告)号：US07633790B2
公开(公告)日：2009-12-15
申请号：US12286723
申请日：2008-10-01
申请人： Darrel Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe J. Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrel Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe J. Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： G11C11/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
摘要翻译：公开了一种包括导电氧化物电极的存储单元。存储单元包括用于将数据存储为多个电阻状态的存储元件。存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。导电氧化物层也可以与金属层（例如Pt）接触。存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

7. 发明授权

US07400006B1 Conductive memory device with conductive oxide electrodes 有权
标题翻译：具有导电氧化物电极的导电存储器件
公开(公告)号：US07400006B1
公开(公告)日：2008-07-15
申请号：US11405958
申请日：2006-04-18
申请人： Darrell Rinerson , Steve Kuo-Ren Hsia , Wayne Kinney , Steven W. Longcor
发明人： Darrell Rinerson , Steve Kuo-Ren Hsia , Wayne Kinney , Steven W. Longcor
IPC分类号： H01L31/062
CPC分类号： H01L27/2418 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/165
摘要： A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.
摘要翻译：提供了使用阻挡电极的多电阻状态元件。如果使用某些材料作为电极，电极可用于多种用途。氧化物和氮化物特别适用于作为阻挡层，甚至可能甚至粘附层和牺牲层。

8. 发明授权

US07330370B2 Enhanced functionality in a two-terminal memory array 有权
标题翻译：两端存储器阵列中增强的功能
公开(公告)号：US07330370B2
公开(公告)日：2008-02-12
申请号：US11021600
申请日：2004-12-23
申请人： Darrell Rinerson , Christophe Chevallier , Steven W. Longcor , Edmond Ward , Robert Norman
发明人： Darrell Rinerson , Christophe Chevallier , Steven W. Longcor , Edmond Ward , Robert Norman
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.
摘要翻译：介绍了增强功能的内存阵列。阵列中的每个单元包括一对存储元件电极。一对存储元件电极上的读取电流表示存储的信息，并且跨该对存储元件电极的不同写入电压电平被用于存储非易失性信息。该阵列具有至少一个增强功能部分，其执行从由参考，纠错，设备特定存储，缺陷映射表和冗余组成的组中选择的操作。

9. 发明授权

US07227775B2 Two terminal memory array having reference cells 有权
标题翻译：具有参考单元的两个终端存储器阵列
公开(公告)号：US07227775B2
公开(公告)日：2007-06-05
申请号：US11478520
申请日：2006-06-29
申请人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor
发明人： Darrell Rinerson , Christophe J. Chevallier , Steven W. Longcor
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
摘要翻译：提供包括参考单元的存储器。存储器具有地址解码电路和非易失性和可重写的存储器单元阵列。每个存储单元具有能够经历电阻变化的两端存储器插头。感应电路将激活的存储单元与参考电平进行比较。参考电平通常由可以在选择存储器单元的同时被选择的至少一个参考单元产生。

10. 发明授权

US07082052B2 Multi-resistive state element with reactive metal 有权
标题翻译：具有反应性金属的多电阻状态元件
公开(公告)号：US07082052B2
公开(公告)日：2006-07-25
申请号：US10773549
申请日：2004-02-06
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： G11C11/14
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译：提供经处理的导电元件。可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。该结构还具有非线性IV特性，这在某些阵列中是有利的。

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