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1. 发明授权

US5661055A Method of making nonvolatile memory cell with vertical gate overlap and zero birds' beaks 失效
标题翻译：制造具有垂直门重叠和零鸟喙的非易失性存储单元的方法
公开(公告)号：US5661055A
公开(公告)日：1997-08-26
申请号：US474610
申请日：1995-06-07
申请人： James Juen Hsu , Steven W. Longcor , Jih-Chang Lien
发明人： James Juen Hsu , Steven W. Longcor , Jih-Chang Lien
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.
摘要翻译：诸如闪存EEPROM的存储器件具有零鸟嘴和垂直重叠的门，以便于EEPROM的核心中的高电池密度。在制造期间，在芯上形成一层场氧化物。通过蚀刻通过场氧化物层暴露有源区域，以在活性区域周围形成垂直壁的空腔。在每个空腔内形成隧道氧化物，浮栅，互间电介质和控制栅极，使得浮栅与垂直壁重叠。结果，保持栅极之间的电容耦合，但是电池的水平尺寸减小。类似地，没有鸟的喙有助于核心中更高的细胞密度。

2. 发明授权

US5680345A Nonvolatile memory cell with vertical gate overlap and zero birds beaks 失效
标题翻译：具有垂直门重叠和零鸟喙的非易失性存储单元
公开(公告)号：US5680345A
公开(公告)日：1997-10-21
申请号：US469953
申请日：1995-06-06
申请人： James Juen Hsu , Steven W. Longcor , Jih-Chang Lien
发明人： James Juen Hsu , Steven W. Longcor , Jih-Chang Lien
IPC分类号： H01L21/8247 , H01L21/265 , H01L21/225
CPC分类号： H01L27/11521
摘要： A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.
摘要翻译：诸如闪存EEPROM的存储器件具有零鸟嘴和垂直重叠的门，以便于EEPROM的核心中的高电池密度。在制造期间，在芯上形成一层场氧化物。通过蚀刻通过场氧化物层暴露有源区域，以在活性区域周围形成垂直壁的空腔。在每个空腔内形成隧道氧化物，浮栅，互间电介质和控制栅极，使得浮栅与垂直壁重叠。结果，保持栅极之间的电容耦合，但是电池的水平尺寸减小。类似地，没有鸟的喙有助于核心中更高的细胞密度。

3. 发明申请

US20140335669A1 EMBEDDED NON-VOLATILE MEMORY 有权
公开(公告)号：US20140335669A1
公开(公告)日：2014-11-13
申请号：US14306801
申请日：2014-06-17
申请人： Daniel R. Shepard , Mac D. Apodaca , Thomas Michael Trent , James Juen Hsu
发明人： Daniel R. Shepard , Mac D. Apodaca , Thomas Michael Trent , James Juen Hsu
IPC分类号： H01L27/24 , H01L45/00 , H01L21/8238
CPC分类号： H01L27/2463 , H01L21/8238 , H01L27/04 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

4. 发明授权

US06858501B2 Self-aligned dual-floating gate memory cell and method for manufacturing the same 有权
标题翻译：自对准双浮栅存储单元及其制造方法
公开(公告)号：US06858501B2
公开(公告)日：2005-02-22
申请号：US10412293
申请日：2003-04-14
申请人： James Juen Hsu
发明人： James Juen Hsu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7887
摘要： An integrated circuit that includes a first dual-floating gate memory cell having a first floating gate isolated from a second floating gate for storing at least one bit of datum, and a second dual-floating gate memory cell having a third floating gate isolated from a fourth floating gate for storing at least one bit of datum, wherein the first dual-floating gate memory cell and the second dual-floating gate memory cell share a control gate, wherein the second floating gate of the first dual-floating gate memory cell shares an oxide layer with the third floating gate of the second dual-floating gate memory cell, and wherein the oxide layer electrically insulates the second and third floating gates from the control gate.
摘要翻译：一种集成电路，其包括具有与第二浮动栅极隔离的第一浮动栅极的第一双浮置栅极存储单元，用于存储至少一个基准点;以及第二双浮置栅极存储单元，具有与第一浮置栅极隔离的第三浮置栅极用于存储至少一位数据的第四浮动栅极，其中所述第一双浮置栅极存储器单元和所述第二双浮置栅极存储器单元共享控制栅极，其中所述第一双浮置栅极存储单元的第二浮置栅极共享具有第二双浮置栅极存储单元的第三浮置栅极的氧化物层，并且其中氧化物层使第二和第三浮置栅极与控制栅极电绝缘。

5. 发明授权

US09054031B2 Embedded non-volatile memory 有权
标题翻译：嵌入式非易失性存储器
公开(公告)号：US09054031B2
公开(公告)日：2015-06-09
申请号：US14306801
申请日：2014-06-17
申请人： Daniel R. Shepard , Mac D. Apodaca , Thomas Michael Trent , James Juen Hsu
发明人： Daniel R. Shepard , Mac D. Apodaca , Thomas Michael Trent , James Juen Hsu
IPC分类号： H01L27/24 , H01L45/00 , H01L21/8238 , H01L27/04 , H01L27/102
CPC分类号： H01L27/2463 , H01L21/8238 , H01L27/04 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.
摘要翻译：本发明是将非易失性存储器并入到需要四个或更少的掩模和有限的附加处理步骤的CMOS工艺中的方法。本发明是在形成MOS晶体管的栅极氧化物并且沉积栅极多晶硅之后引入到标准CMOS工艺（i）中的外延硅或多晶硅工艺序列（从而保护晶体管的精细表面积 MOS晶体管）和（ii）在形成与这些MOS晶体管的接触水银之前（因此，在进行二氧化硅的形成之前，执行任何新引入的具有升高温度的步骤，例如用于形成二极管的任何外延硅或多晶硅沉积）形成那个自杀者）。使用二极管矩阵实现4F2存储器阵列，其中二极管以垂直取向形成。

6. 发明授权

US06862219B2 Weak programming method of non-volatile memory 有权
标题翻译：非易失性存储器编程方法薄弱
公开(公告)号：US06862219B2
公开(公告)日：2005-03-01
申请号：US10249140
申请日：2003-03-19
申请人： Shih-Hsien Yang , Chien-Min Wu , James Juen Hsu , Chi-Moon Huang
发明人： Shih-Hsien Yang , Chien-Min Wu , James Juen Hsu , Chi-Moon Huang
IPC分类号： G11C11/34 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3477 , G11C16/3404 , G11C16/3409
摘要： A weak programming method of a non-volatile memory. A first voltage is applied to a substrate during a first duration, while a control-gate voltage, such as zero volt, is applied to the gate, such that the leakage of the bit line is reduced and electron-hole pairs are generated. In the second duration, a second voltage is applied to the substrate, and a third voltage is applied to the gate to enhance the capability of injecting electrons into the floating gate of the non-volatile memory. Therefore, the distribution of the threshold voltage is more concentrated. The second voltage has a polarity the same as that of the first voltage, while the polarity of the third voltage is opposite to that of the second voltage.
摘要翻译：非易失性存储器的弱编程方法。在第一持续时间内将第一电压施加到衬底，同时将诸如零伏特的控制栅极电压施加到栅极，使得位线的泄漏减小并且产生电子 - 空穴对。在第二持续时间中，向衬底施加第二电压，并且向栅极施加第三电压以增强将电子注入非易失性存储器的浮动栅极的能力。因此，阈值电压的分布更为集中。第二电压具有与第一电压相同的极性，而第三电压的极性与第二电压的极性相反。

7. 发明授权

US06969686B2 Memory device having isolation trenches with different depths and the method for making the same 有权
标题翻译：具有不同深度的隔离沟槽的存储器件及其制造方法
公开(公告)号：US06969686B2
公开(公告)日：2005-11-29
申请号：US10353177
申请日：2003-01-28
申请人： Wen-Kuei Hsieh , Chih-Mu Huang , James Juen Hsu
发明人： Wen-Kuei Hsieh , Chih-Mu Huang , James Juen Hsu
IPC分类号： H01L21/308 , H01L21/762 , H01L21/8239 , H01L27/105 , H01L21/302
CPC分类号： H01L27/105 , H01L21/3081 , H01L21/76229 , H01L27/1052
摘要： A method for manufacturing a memory device utilizes multi-etching processes to respectively construct isolation trenches in a memory substrate that has a memory array area and a peripheral circuit region, wherein the depth of the trenches in the peripheral circuit region is deeper into the memory substrate than the depth of the trenches in the memory array area. Therefore, possible current leakage caused from the high operating voltage is effectively mitigated, and the performance of the memory device is increased.
摘要翻译：一种用于制造存储器件的方法利用多次蚀刻工艺来分别在具有存储器阵列区域和外围电路区域的存储器衬底中构建隔离沟槽，其中外围电路区域中的沟槽的深度更深于存储器衬底比存储器阵列区域中的沟槽的深度高。因此，可以有效地缓解由高工作电压引起的可能的电流泄漏，并且提高存储器件的性能。

8. 发明授权

US06700165B1 Semiconductor structure with the common source line 有权
标题翻译：半导体结构具有共同的源极线
公开(公告)号：US06700165B1
公开(公告)日：2004-03-02
申请号：US10279795
申请日：2002-10-25
申请人： Po-An Chen , James Juen Hsu
发明人： Po-An Chen , James Juen Hsu
IPC分类号： H01L2976
CPC分类号： H01L27/105 , H01L27/1052
摘要： A semiconductor structure with common source line, the semiconductor structure has two word lines, some bit lines, a silicon-based layer and a suicide layer. The silicon-based layer is located between and electrically separated from these word lines, but is electrically coupled with these bit lines. The silicide layer is located over and electrically coupled with the silicon-based layer. Moreover, suicide layer and silicide layer could be replaced by a silicon-base conductor layer, and are directly electrically coupled with some separated doped regions that located inside a substrate.
摘要翻译：具有共同源极线的半导体结构，半导体结构具有两条字线，一些位线，硅基层和硅化物层。硅基层位于这些字线之间并且与这些字线电分离，但是与这些位线电耦合。硅化物层位于硅基层上并与硅基层电耦合。此外，硅化物层和硅化物层可以由硅基导体层替代，并且与位于衬底内部的一些分离的掺杂区域直接电耦合。

9. 发明授权

US5656513A Nonvolatile memory cell formed using self aligned source implant 失效
标题翻译：使用自对准源植入物形成的非易失性存储单元
公开(公告)号：US5656513A
公开(公告)日：1997-08-12
申请号：US474879
申请日：1995-06-07
申请人： Hsingya Arthur Wang , James Juen Hsu
发明人： Hsingya Arthur Wang , James Juen Hsu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A memory device, such as a flash EEPROM, employs a high energy implantation to form common source line, avoiding the necessity of self-aligned source etch processes. The use of the high energy implantation, and avoiding the etching process, provides for greater cell uniformity, and better V.sub.T distribution.
摘要翻译：诸如闪存EEPROM的存储器件采用高能量注入来形成公共源极线，避免了自对准源蚀刻工艺的需要。使用高能量注入和避免蚀刻工艺提供更大的电池均匀性和更好的VT分布。

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