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    • 1. 发明授权
    • Voltage regulator for line powered linear and switching power supply
    • 用于线路电源线性和开关电源的稳压器
    • US06856103B1
    • 2005-02-15
    • US10665049
    • 2003-09-17
    • James E. HudsonThomas J. Mayer
    • James E. HudsonThomas J. Mayer
    • H05B39/02H05B39/04G05F1/00
    • H05B39/02H05B39/045Y02B20/142
    • The invented voltage regulator is a solid state low voltage regulator for quartz halogen or low voltage incandescent lamps and quartz halogen or low voltage incandescent lamp or LED array circuits wherein the volt regulator reduces a conventional mains power line source of, for example, a 115 volt AC to 480 V AC power source, to within a range of from 11.0 volts to 12.5 volts, preferably 11.6 volts, wherein the lamps, and LED arrays have consistent color, consistent light output, the lamp filaments and LED arrays are exposed to soft start operating currents and lamp and array life can be increased. The voltage regulator utilizes an AC rectifier circuit to provide a pulsing DC voltage, a DC voltage sensing circuit, a soft start oscillator circuit, an internal DC voltage oscillator reference circuit and an AC power line control circuit.
    • 本发明的电压调节器是用于石英卤素灯或低压白炽灯和石英卤素灯或低压白炽灯或LED阵列电路的固态低压调节器,其中电压调节器将常规电源线路源例如为115伏特 AC至480 V交流电源,范围为11.0 V至12.5 V,优选为11.6 V,其中灯和LED阵列具有一致的颜色,一致的光输出,灯丝和LED阵列暴露于软启动 可以提高工作电流和灯管寿命。 电压调节器利用AC整流电路提供脉冲直流电压,直流电压检测电路,软启动振荡电路,内部直流电压振荡器参考电路和交流电源线控制电路。
    • 3. 发明申请
    • DEFECT ANALYZER
    • 缺陷分析仪
    • US20110251713A1
    • 2011-10-13
    • US13166547
    • 2011-06-22
    • JANET TESHIMADaniel E. PartinJames E. Hudson
    • JANET TESHIMADaniel E. PartinJames E. Hudson
    • G06F19/00
    • H01J37/28H01J37/302H01J37/304H01J37/3056H01J2237/24592H01J2237/2485H01J2237/2817H01J2237/31745H01L21/67253H01L21/67276
    • The present invention provides methods, devices, and systems for analyzing defects in an object such as a semiconductor wafer. In one embodiment, it provides a method of characterizing defects in semiconductor wafers during fabrication in a semiconductor fabrication facility. This method comprises the following actions. The semiconductor wafers are inspected to locate defects. Locations corresponding to the located defects are then stored in a defect file. A dual charged-particle beam system is automatically navigated to the vicinity defect location using information from the defect file. The defect is automatically identified and a charged particle beam image of the defect is then obtained. The charged particle beam image is then analyzed to characterize the defect. A recipe is then determined for further analysis of the defect. The recipe is then automatically executed to cut a portion of the defect using a charged particle beam. The position of the cut is based upon the analysis of the charged particle beam image. Ultimately, a surface exposed by the charged particle beam cut is imaged to obtain additional information about the defect.
    • 本发明提供了用于分析诸如半导体晶片的物体中的缺陷的方法,装置和系统。 在一个实施例中,其提供了在半导体制造设备中制造期间表征半导体晶片中的缺陷的方法。 该方法包括以下动作。 检查半导体晶片以定位缺陷。 然后将与定位的缺陷相对应的位置存储在缺陷文件中。 使用来自缺陷文件的信息,双电荷粒子束系统被自动导航到附近的缺陷位置。 自动识别缺陷,得到缺陷的带电粒子束图像。 然后分析带电粒子束图像以表征缺陷。 然后确定配方以进一步分析缺陷。 然后自动执行配方以使用带电粒子束切割缺陷的一部分。 切割的位置是基于带电粒子束图像的分析。 最终,通过带电粒子束切割暴露的表面被成像以获得关于缺陷的附加信息。
    • 4. 发明申请
    • DEFECT ANALYZER
    • 缺陷分析仪
    • US20090230303A1
    • 2009-09-17
    • US12348771
    • 2009-01-05
    • Janet TeshimaDaniel E. PartinJames E. Hudson
    • Janet TeshimaDaniel E. PartinJames E. Hudson
    • G21K7/00G01N23/00
    • H01J37/28H01J37/302H01J37/304H01J37/3056H01J2237/24592H01J2237/2485H01J2237/2817H01J2237/31745H01L21/67253H01L21/67276
    • The present invention provides methods, devices, and systems for analyzing defects in an object such as a semiconductor wafer. In one embodiment, it provides a method of characterizing defects in semiconductor wafers during fabrication in a semiconductor fabrication facility. This method comprises the following actions. The semiconductor wafers are inspected to locate defects. Locations corresponding to the located defects are then stored in a defect file. A dual charged-particle beam system is automatically navigated to the vicinity defect location using information from the defect file. The defect is automatically identified and a charged particle beam image of the defect is then obtained. The charged particle beam image is then analyzed to characterize the defect. A recipe is then determined for further analysis of the defect. The recipe is then automatically executed to cut a portion of the defect using a charged particle beam. The position of the cut is based upon the analysis of the charged particle beam image. Ultimately, a surface exposed by the charged particle beam cut is imaged to obtain additional information about the defect.
    • 本发明提供了用于分析诸如半导体晶片的物体中的缺陷的方法,装置和系统。 在一个实施例中,其提供了在半导体制造设备中制造期间表征半导体晶片中的缺陷的方法。 该方法包括以下动作。 检查半导体晶片以定位缺陷。 然后将与定位的缺陷相对应的位置存储在缺陷文件中。 使用来自缺陷文件的信息,双电荷粒子束系统被自动导航到附近的缺陷位置。 自动识别缺陷,得到缺陷的带电粒子束图像。 然后分析带电粒子束图像以表征缺陷。 然后确定配方以进一步分析缺陷。 然后自动执行配方以使用带电粒子束切割缺陷的一部分。 切割的位置是基于带电粒子束图像的分析。 最终,通过带电粒子束切割暴露的表面被成像以获得关于缺陷的附加信息。
    • 8. 发明授权
    • Defect analyzer
    • 缺陷分析仪
    • US08249828B2
    • 2012-08-21
    • US13166547
    • 2011-06-22
    • Janet TeshimaDaniel E. PartinJames E. Hudson
    • Janet TeshimaDaniel E. PartinJames E. Hudson
    • G01R27/28
    • H01J37/28H01J37/302H01J37/304H01J37/3056H01J2237/24592H01J2237/2485H01J2237/2817H01J2237/31745H01L21/67253H01L21/67276
    • The present invention provides methods, devices, and systems for analyzing defects in an object such as a semiconductor wafer. In one embodiment, it provides a method of characterizing defects in semiconductor wafers during fabrication in a semiconductor fabrication facility. This method comprises the following actions. The semiconductor wafers are inspected to locate defects. Locations corresponding to the located defects are then stored in a defect file. A dual charged-particle beam system is automatically navigated to the vicinity defect location using information from the defect file. The defect is automatically identified and a charged particle beam image of the defect is then obtained. The charged particle beam image is then analyzed to characterize the defect. A recipe is then determined for further analysis of the defect. The recipe is then automatically executed to cut a portion of the defect using a charged particle beam. The position of the cut is based upon the analysis of the charged particle beam image. Ultimately, a surface exposed by the charged particle beam cut is imaged to obtain additional information about the defect.
    • 本发明提供了用于分析诸如半导体晶片的物体中的缺陷的方法,装置和系统。 在一个实施例中,其提供了在半导体制造设备中制造期间表征半导体晶片中的缺陷的方法。 该方法包括以下动作。 检查半导体晶片以定位缺陷。 然后将与定位的缺陷相对应的位置存储在缺陷文件中。 使用来自缺陷文件的信息,双电荷粒子束系统被自动导航到附近的缺陷位置。 自动识别缺陷,得到缺陷的带电粒子束图像。 然后分析带电粒子束图像以表征缺陷。 然后确定配方以进一步分析缺陷。 然后自动执行配方以使用带电粒子束切割缺陷的一部分。 切割的位置是基于带电粒子束图像的分析。 最终,通过带电粒子束切割暴露的表面被成像以获得关于缺陷的附加信息。