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1. 发明申请

US20050038943A1 Bus precharge during a phase of a clock signal to eliminate idle clock cycle 失效
标题翻译：在一个时钟信号的相位期间，总线预充电以消除空闲时钟周期
公开(公告)号：US20050038943A1
公开(公告)日：2005-02-17
申请号：US10950082
申请日：2004-09-24
申请人： James Cho , Joseph Rowlands , Mark Pearce
发明人： James Cho , Joseph Rowlands , Mark Pearce
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/423 , G06F13/4077
摘要： A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.
摘要翻译：系统包括总线和用于预充电总线的电路。电路可以被耦合以接收与总线相关联的时钟信号，并且可以被配置为在时钟信号的周期的间隔期间对总线进行预充电，该间隔在第一边沿（上升沿或下降沿）之间以及随后的边沿（下降或上升）。该周期内的第二间隔并且不包括间隔可用于执行总线传送。以这种方式，可以在相同的时钟周期中执行预充电和传输两者。可以改善总线的带宽，因为可以在每个时钟周期发生传输，而不是具有用于预充电的非传输时钟周期。

2. 发明申请

US20050027911A1 System on a chip for networking 有权
标题翻译：系统在芯片上进行网络连接
公开(公告)号：US20050027911A1
公开(公告)日：2005-02-03
申请号：US10884700
申请日：2004-07-02
申请人： Mark Hayter , Joseph Rowlands , James Cho
发明人： Mark Hayter , Joseph Rowlands , James Cho
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/387
摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.
摘要翻译：用于网络设备的芯片上的系统。在一个实现中，芯片上的系统可以包括（集成到单个集成电路），处理器和用于联网应用的一个或多个I / O设备。例如，I / O设备可以包括用于耦合到网络接口的一个或多个网络接口电路。在一个实施例中，一致性可以在芯片上的系统的边界内被强制执行，但是在边界之外不被强制执行。

3. 发明授权

US08225315B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US08225315B1
公开(公告)日：2012-07-17
申请号：US11933319
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
IPC分类号： G06F9/455 , G06F15/76
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.
摘要翻译：一种包括物理核心和第一虚拟核心的虚拟核心管理系统，包括与执行第一程序相关联的逻辑状态的集合。第一个虚拟内核映射到物理内核。虚拟核心管理系统还包括第二虚拟核心，其包括与执行第二程序相关联的逻辑状态的集合，虚拟核心管理组件被配置为从物理核心取消映射第一虚拟核心并将第二虚拟核心映射到响应虚拟核心管理组件检测物理内核空闲的物理核心。

4. 发明授权

US09130856B2 Creating multiple NoC layers for isolation or avoiding NoC traffic congestion 有权
标题翻译：创建多个NoC层进行隔离或避免NoC流量拥塞
公开(公告)号：US09130856B2
公开(公告)日：2015-09-08
申请号：US13752226
申请日：2013-01-28
申请人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
发明人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
IPC分类号： G01R31/08 , H04L12/803
CPC分类号： H04L47/125 , H04L45/66 , H04L47/70
摘要： Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.
摘要翻译：本文描述的系统和方法涉及基于网络片上（NoC）互连的解决方案，其基于系统业务流的带宽要求，自动且动态地确定NoC互连系统中所需的层数。通过在映射不同NoC层的信道和路由之间的业务流的负载分担来动态分配和最小化层数。可以分配附加层以提供可能需要用于死锁避免的附加虚拟通道并且维持各种系统流之间的隔离属性。可以一起执行用于附加带宽和附加虚拟通道（VC）的层分配。

5. 发明授权

US07814298B1 Promoting and appending traces in an instruction processing circuit based upon a bias value 有权
标题翻译：基于偏置值在指令处理电路中促进和追加迹线
公开(公告)号：US07814298B1
公开(公告)日：2010-10-12
申请号：US11941883
申请日：2007-11-16
申请人： Richard Thaik , John Gregory Favor , Joseph Rowlands , Leonard Eric Shar , Matthew Ashcraft
发明人： Richard Thaik , John Gregory Favor , Joseph Rowlands , Leonard Eric Shar , Matthew Ashcraft
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , Y02D10/13
摘要： A method, system and computer program product for promoting a trace in an instruction processing circuit is disclosed. They comprise determining if a current trace is promotable and determining if a next trace is appendable to the current trace. They include promoting the current trace and the next trace if the current trace is promotable and the next trace is appendable.
摘要翻译：公开了一种用于促进指令处理电路中的迹线的方法，系统和计算机程序产品。它们包括确定当前跟踪是否可提升，并确定下一个跟踪是否可附加到当前跟踪。它们包括在当前跟踪是可升级的并且下一个跟踪是可附加的情况下促进当前跟踪和下一个跟踪。

6. 发明授权

US07797563B1 System and method for conserving power 有权
标题翻译：节电功能的系统和方法
公开(公告)号：US07797563B1
公开(公告)日：2010-09-14
申请号：US11450103
申请日：2006-06-09
申请人： Laurent R. Moll , Joseph Rowlands
发明人： Laurent R. Moll , Joseph Rowlands
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： A system includes a plurality of processors and a monitor coupled to each of the plurality of processors. The monitor is located in a location separate from the plurality of processors. At least some portions of one or more of the plurality of processors enter a power-conservation mode after the one or more of the plurality of processors request one or more resources. The system further includes a power-management controller. The power-management controller is operative to cause the at least some portions of the one or more of the plurality of processors to enter the power-conservation mode after the one or more of the plurality of processors request the one or more resources.
摘要翻译：系统包括多个处理器和耦合到多个处理器中的每一个的监视器。显示器位于与多个处理器分离的位置。所述多个处理器中的一个或多个处理器的至少一些部分在所述多个处理器中的一个或多个处理器请求一个或多个资源之后进入功率保存模式。该系统还包括一个电源管理控制器。功率管理控制器可操作以在所述多个处理器中的一个或多个处理器请求所述一个或多个资源之后，使所述多个处理器中的一个或多个处理器的所述至少一些部分进入所述功率保存模式。

7. 发明申请

US20050081127A1 Hypertransport exception detection and processing 有权
标题翻译：超传输异常检测和处理
公开(公告)号：US20050081127A1
公开(公告)日：2005-04-14
申请号：US10684953
申请日：2003-10-14
申请人： Joseph Rowlands , Laurent Moll
发明人： Joseph Rowlands , Laurent Moll
IPC分类号： G06F11/00 , G06F11/27
CPC分类号： G06F11/0784 , G06F11/0724 , G06F11/0745 , G06F11/2242
摘要： In accordance with the present invention a system for detecting transaction errors in a system comprising a plurality of data processing devices using a common system interconnect bus, comprises a node controller operably connected to said system interconnect bus and a plurality of interface agents communicatively coupled to said node controller. Error corresponding to transactions between said interface agents and other processing modules in said system are directed to said node controller; and wherein transaction errors that would not normally be communicated to said system interconnect bus are communicated by said node controller to said system interconnect bus to be available for detection. In an embodiment of the present invention, the interface agents operate in accordance with the hypertransport protocol. A system control and debug unit and a trace cache operably connected to the system bus can be used to diagnose and store errors conditions.
摘要翻译：根据本发明，一种用于检测包括使用公共系统互连总线的多个数据处理设备的系统中的事务错误的系统包括可操作地连接到所述系统互连总线的节点控制器和通信地耦合到所述系统互连总线的多个接口代理节点控制器。与所述接口代理和所述系统中的其他处理模块之间的事务相对应的错误被引导到所述节点控制器; 并且其中通常不会传送到所述系统互连总线的事务错误由所述节点控制器传送到所述系统互连总线以供检测。在本发明的实施例中，接口代理根据超传输协议进行操作。可操作地连接到系统总线的系统控制和调试单元和跟踪缓存可用于诊断和存储错误状况。

8. 发明申请

US20050080948A1 Bridges performing remote reads and writes as uncacheable coherent 失效
标题翻译：执行远程读取和写入的桥梁不可缓解
公开(公告)号：US20050080948A1
公开(公告)日：2005-04-14
申请号：US10685136
申请日：2003-10-14
申请人： Joseph Rowlands
发明人： Joseph Rowlands
IPC分类号： G06F3/00 , G06F12/08 , G06F13/40
CPC分类号： G06F13/4027 , G06F12/0813 , G06F12/0815 , G06F2212/621
摘要： A system and method for improving the bandwidth for data read and write operations in a multi-node system by using uncacheable read and write commands to a home node in the multi-node system so that the home node can determine whether the commands needs to enter the coherent memory space. In one embodiment where nodes are connected via HT interfaces, posted commands are used to transmit uncacheable write commands over the HT fabric to a remote home node so that no response is required from the home node. When both cacheable and uncacheable memory operations are mixed in a multi-node system, a producer-consumer software model may be used to require that the data and flag must be co-located in the home node's memory and that the producer write both the data and flag using regular HT I/O commands. In one embodiment, a system for managing data in multiple data processing devices using common data paths comprises a first data processing system comprising a memory, wherein the memory comprises a cacheable coherent memory space; and a second data processing system communicatively coupled to the first data processing system with the second data processing system comprising at least one bridge, wherein the bridge is operable to perform an uncacheable remote access to the cacheable coherent memory space of the first data processing system. In some embodiments, the access performed by the bridge comprises a data write to the memory of the first data processing system for incorporation into the cacheable coherent memory space of the first data system. In other embodiments, the access performed by the bridge comprises a data read from the cacheable coherent memory space of the first data system.
摘要翻译：一种用于通过对多节点系统中的家庭节点使用不可缓存的读写命令来改善多节点系统中数据读写操作的带宽的系统和方法，使得家节点可以确定命令是否需要进入相干记忆空间。在通过HT接口连接节点的一个实施例中，发布的命令用于通过HT结构向远程家庭节点发送不可写入的写入命令，使得不需要来自家庭节点的响应。当在多节点系统中混合可缓存和不可缓存的存储器操作时，可以使用生产者 - 消费者软件模型来要求数据和标志必须位于家庭节点的存储器中，并且生产者将数据写入并使用常规HT I / O命令进行标志。在一个实施例中，用于使用公共数据路径管理多个数据处理设备中的数据的系统包括包括存储器的第一数据处理系统，其中所述存储器包括可高速缓存的相干存储器空间; 以及第二数据处理系统，其通信地耦合到所述第一数据处理系统，所述第二数据处理系统包括至少一个桥，其中所述桥可操作以对所述第一数据处理系统的所述可高速缓存的相干存储器空间执行不可缓存的远程访问。在一些实施例中，由桥执行的访问包括对第一数据处理系统的存储器的数据写入，用于结合到第一数据系统的可高速缓存的相干存储器空间中。在其他实施例中，由桥执行的访问包括从第一数据系统的可高速缓存的相干存储器空间读取的数据。

9. 发明公开

US20230315483A1 PROCESSOR CORE SUBSYSTEM WITH OPEN-STANDARD NETWORK-ON-CHIP PORTS 审中-公开
公开(公告)号：US20230315483A1
公开(公告)日：2023-10-05
申请号：US17712106
申请日：2022-04-02
申请人： Shih Jun Chong , Ignacio Celis , Krishnakumar Ganapathy , Sang Kim , Chuan Yin Loo , Sanjoy K. Mondal , Mukesh Patel , Arvind Raman , Joseph Rowlands , Shankar Narayanan Venkat Ramani
发明人： Shih Jun Chong , Ignacio Celis , Krishnakumar Ganapathy , Sang Kim , Chuan Yin Loo , Sanjoy K. Mondal , Mukesh Patel , Arvind Raman , Joseph Rowlands , Shankar Narayanan Venkat Ramani
IPC分类号： G06F9/4401 , G06F9/48 , G06F9/38 , G06F9/30
CPC分类号： G06F9/4405 , G06F9/4887 , G06F9/3877 , G06F9/30123
摘要： Embodiments of apparatuses, methods, and machine-readable mediums for a subsystem with open-standard network-on-chip ports are disclosed. In an embodiment, a machine-readable medium includes a design of an apparatus to be manufactured, the apparatus to include one or more cores, and a network-on-chip having at least one port of a first type and at least one port of a second type. The first type is to communicate with the one or more cores according to a proprietary protocol. The second type is to communicate with an intellectual property block according to an open-standard protocol.

10. 发明授权

US09253085B2 Hierarchical asymmetric mesh with virtual routers 有权
标题翻译：虚拟路由器的层次化非对称网格
公开(公告)号：US09253085B2
公开(公告)日：2016-02-02
申请号：US13723732
申请日：2012-12-21
申请人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
发明人： Sailesh Kumar , Eric Norige , Joji Philip , Mahmud Hassan , Sundari Mitra , Joseph Rowlands
IPC分类号： H04L12/775 , H04L12/715
CPC分类号： H04L45/58 , H04L45/04
摘要： A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.
摘要翻译：片上网络配置包括以二维网格布置的第一多个核心; 第一多个路由器，所述第一多个路由器中的每一个与所述第一多个核中的相应的本地路由器相关联，所述第一多个路由器中的每一个具有多个定向端口，所述多个定向端口被配置为提供到所述第一多个核心中的其他核心的路由器设置在所述二维网状布置的周围的第二多个芯; 以及第二多个路由器，所述第二多个路由器中的每一个与所述第二多个核中的对应的本地核心相关联，并且具有被配置为提供到所述第一多个路由器中的相邻路由器的连接的定向端口。

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