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1. 发明授权

US07814298B1 Promoting and appending traces in an instruction processing circuit based upon a bias value 有权
标题翻译：基于偏置值在指令处理电路中促进和追加迹线
公开(公告)号：US07814298B1
公开(公告)日：2010-10-12
申请号：US11941883
申请日：2007-11-16
申请人： Richard Thaik , John Gregory Favor , Joseph Rowlands , Leonard Eric Shar , Matthew Ashcraft
发明人： Richard Thaik , John Gregory Favor , Joseph Rowlands , Leonard Eric Shar , Matthew Ashcraft
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , Y02D10/13
摘要： A method, system and computer program product for promoting a trace in an instruction processing circuit is disclosed. They comprise determining if a current trace is promotable and determining if a next trace is appendable to the current trace. They include promoting the current trace and the next trace if the current trace is promotable and the next trace is appendable.
摘要翻译：公开了一种用于促进指令处理电路中的迹线的方法，系统和计算机程序产品。它们包括确定当前跟踪是否可提升，并确定下一个跟踪是否可附加到当前跟踪。它们包括在当前跟踪是可升级的并且下一个跟踪是可附加的情况下促进当前跟踪和下一个跟踪。

2. 发明授权

US08015359B1 Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit 有权
标题翻译：用于在指令处理电路中利用公共结构进行跟踪验证和维持一致性的方法和系统
公开(公告)号：US08015359B1
公开(公告)日：2011-09-06
申请号：US11782238
申请日：2007-07-24
申请人： John Gregory Favor , Joseph Rowlands , Leonard Eric Shar , Richard Thaik
发明人： John Gregory Favor , Joseph Rowlands , Leonard Eric Shar , Richard Thaik
IPC分类号： G06F13/00
CPC分类号： G06F12/0815 , G06F9/3017 , G06F9/322 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F9/3844 , G06F12/0875 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： An instruction processing circuit for a processor is disclosed. The instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution unit of the processor. The instruction processing circuit comprises at least one cache circuit and the processing circuit includes a sequencer and a page translation buffer coupled to the sequencer for trace verification and maintaining coherency between a memory and the at least one cache.
摘要翻译：公开了一种用于处理器的指令处理电路。指令处理电路适于基于一个或多个指令序列向处理器的执行单元提供一个或多个操作序列。所述指令处理电路包括至少一个高速缓存电路，并且所述处理电路包括定序器和耦合到所述定序器的页面翻译缓冲器，用于跟踪验证并维持存储器与所述至少一个高速缓存之间的一致性。

3. 发明授权

US08032710B1 System and method for ensuring coherency in trace execution 有权
标题翻译：用于确保跟踪执行中的一致性的系统和方法
公开(公告)号：US08032710B1
公开(公告)日：2011-10-04
申请号：US11782163
申请日：2007-07-24
申请人： Matthew Ashcraft , John Gregory Favor , Joseph Rowlands , Leonard E. Shar , Richard Thaik
发明人： Matthew Ashcraft , John Gregory Favor , Joseph Rowlands , Leonard E. Shar , Richard Thaik
IPC分类号： G06F13/00
CPC分类号： G06F9/30072 , G06F9/3804 , G06F9/3808 , G06F9/3812 , G06F9/3836
摘要： A method and system of ensuring coherency of a sequence of instructions to be executed by a processor having a trace unit and an execution unit includes grouping at least a portion of the sequence of instructions to form at least one trace where a status of the at least one trace is set to a verified status when the at least one trace is formed; holding in the at least one trace a coherency component that includes a pointer to a physical address of the at least one trace; receiving, based on the coherency component, the pointer to the physical address as associated with an invalidating event, and in response thereto, setting the status of the at least one trace to be an unverified status; and preventing the at least one trace from being executed when the status of the at least one trace is the unverified status.
摘要翻译：一种确保要由具有跟踪单元和执行单元的处理器执行的指令序列的一致性的方法和系统包括对指令序列的至少一部分进行分组，以形成至少一个跟踪，其中该至少一个状态至少当形成至少一条迹线时，将一条迹线设置为已验证状态; 在所述至少一个跟踪中保持包括指向所述至少一个跟踪的物理地址的指针的相关性组件; 基于所述一致性分量接收与无效事件相关联的到所述物理地址的指针，并且响应于此，将所述至少一个跟踪的状态设置为未验证状态; 以及当所述至少一个跟踪的状态是未验证状态时，防止所述至少一个跟踪被执行。

4. 发明授权

US07941607B1 Method and system for promoting traces in an instruction processing circuit 有权
标题翻译：用于在指令处理电路中促进迹线的方法和系统
公开(公告)号：US07941607B1
公开(公告)日：2011-05-10
申请号：US11782140
申请日：2007-07-24
申请人： Richard Thaik , John Gregory Favor , Joseph Rowlands , Leonard E. Shar , Matthew William Ashcraft
发明人： Richard Thaik , John Gregory Favor , Joseph Rowlands , Leonard E. Shar , Matthew William Ashcraft
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： A method and system for promoting traces in an instruction processing circuit is disclosed. The method and system comprises determining if a current trace is promotable; and adding the current trace to a sequence buffer if the current trace is promotable. The current trace is marked as promoted and the current trace is marked as a first trace of a multi-block trace. The method and system includes determining if a next trace is promotable; adding the next trace to the sequence buffer if the next trace is promotable; and repeating the above until the next trace is not promotable and then adding the next trace to the sequence buffer if the next trace is not promotable.
摘要翻译：公开了一种用于在指令处理电路中促进迹线的方法和系统。所述方法和系统包括确定当前迹线是否可促进; 并且如果当前跟踪是可升级的，则将当前跟踪添加到序列缓冲器。当前跟踪被标记为提升，当前跟踪被标记为多块跟踪的第一个跟踪。所述方法和系统包括确定下一个跟踪是否可提升; 将下一个跟踪添加到序列缓冲区，如果下一个跟踪是可升级的; 并重复上述操作，直到下一个跟踪不可升级，然后如果下一个跟踪不可升级，则将下一个跟踪添加到序列缓冲区。

5. 再颁专利

USRE39395E1 Data communication network with transfer port, cascade port and/or frame synchronizing signal 有权
标题翻译：具有传输端口，级联端口和/或帧同步信号的数据通信网络
公开(公告)号：USRE39395E1
公开(公告)日：2006-11-14
申请号：US09173582
申请日：1998-10-15
申请人： Geetha N. K. Rangan , Debra J. Worsley , Richard Thaik , Brian C. Edem
发明人： Geetha N. K. Rangan , Debra J. Worsley , Richard Thaik , Brian C. Edem
IPC分类号： H04J3/14
CPC分类号： H04L12/44 , H04L12/6418 , H04L2012/644 , H04L2012/6454 , H04L2012/6459
摘要： A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. An efficient encoding scheme permits transmission of both isochronous and non-isochronous data over existing media, such as twisted pair, without degrading bandwidth previously achieved for non-isochronous data over the same media, such as using an ethernet system. Bandwidth available for a particular isochronous source/sink is selectable and sustainable with a predefined granularity. The arriving data is de-multiplexed at the hub into separate channels for handling the separate streams by appropriate hardware. Preferably, the present invention can be implemented in a fashion that is transparent to already-installed media access controllers. Preferably, some components of the system can detect the frame-transmission capability of other components and, if such capability is lacking, can fall back to a mode compliant with existing capabilities.
摘要翻译：诸如局域网的数据通信系统被提供有传输同步数据的能力。优选地，系统通过以四位半字节的方式将数据进行时分复用为循环帧结构来传送同步数据和非等时数据。有效的编码方案允许在诸如双绞线之类的现有介质上传输同步和非等时同步数据，而不会降低先前通过同一介质（例如使用以太网系统）对非同步数据实现的带宽。可用于特定等时源/汇的带宽可以预定义的粒度来选择和持续。到达的数据在集线器处被解复用为单独的信道，以通过适当的硬件来处理单独的流。优选地，本发明可以以对已经安装的媒体访问控制器透明的方式来实现。优选地，系统的一些组件可以检测其他组件的帧传输能力，并且如果缺乏这种能力，则可以回到符合现有能力的模式。

6. 发明授权

US5566169A Data communication network with transfer port, cascade port and/or frame synchronizing signal 失效
公开(公告)号：US5566169A
公开(公告)日：1996-10-15
申请号：US147359
申请日：1993-11-01
申请人： Geetha N. K. Rangan , Debra J. Worsley , Richard Thaik , Brian C. Edem
发明人： Geetha N. K. Rangan , Debra J. Worsley , Richard Thaik , Brian C. Edem
IPC分类号： F02B75/02 , H04L12/44 , H04L12/64 , H04J3/14
CPC分类号： H04L12/44 , H04L12/6418 , F02B2075/025 , H04L2012/644 , H04L2012/6454 , H04L2012/6459
摘要： A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. An efficient encoding scheme permits transmission of both isochronous and non-isochronous data over existing media, such as twisted pair, without degrading bandwidth previously achieved for non-isochronous data over the same media, such as using an ethernet system. Bandwidth available for a particular isochronous source/sink is selectable and sustainable with a predefined granularity. The arriving data is de-multiplexed at the hub into separate channels for handling the separate streams by appropriate hardware. Preferably, the present invention can be implemented in a fashion that is transparent to already-installed media access controllers. Preferably, some components of the system can detect the frame-transmission capability of other components and, if such capability is lacking, can fall back to a mode compliant with existing capabilities.

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