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1. 发明授权

US06209081B1 Method and system for nonsequential instruction dispatch and execution in a superscalar processor system 失效
标题翻译：在超标量处理器系统中用于非顺序指令调度和执行的方法和系统
公开(公告)号：US06209081B1
公开(公告)日：2001-03-27
申请号：US08255130
申请日：1994-06-07
申请人： James Allan Kahle , Donald Emil Waldecker
发明人： James Allan Kahle , Donald Emil Waldecker
IPC分类号： G06F1500
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/384 , G06F9/3861 , G06F9/3863
摘要： A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer. An indication of the status of each instruction is maintained within a completion buffer and thereafter utilized to selectively transfer results within the intermediate storage buffers to selected general purpose registers in an order consistent with an application specified sequential order. The occurrence of an interrupt which prohibits completion of a selected instruction can therefore be accurately identified within the completion buffer.
摘要翻译：一种用于在超标量处理器系统中允许非顺序指令调度的方法和系统，其在机会性的基础上将顺序排列的多个指令同时分派到一组执行单元，以便在指定的通用寄存器内执行和将其结果放置。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用的执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，从而允许执行每个指令的结果存储在中间存储缓冲区中。每个指令的状态的指示保持在完成缓冲器内，然后用于以与应用指定的顺序顺序一致的顺序将中间存储缓冲器内的结果选择性地传送到所选通用寄存器。因此，可以在完成缓冲器内准确地识别出禁止完成所选指令的中断的发生。

2. 发明授权

US5898882A Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage 失效
标题翻译：利用独立访问的中间存储器在超标量处理器系统中增强指令调度的方法和系统
公开(公告)号：US5898882A
公开(公告)日：1999-04-27
申请号：US1865
申请日：1993-01-08
申请人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
发明人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
IPC分类号： G06F9/38 , G06F15/16
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855
摘要： A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
摘要翻译：一种用于在超标量处理器系统中允许单周期指令调度的方法和系统，其将多个指令同时分配到一组执行单元以执行并将其结果放置在指定的通用寄存器内。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，允许在单个周期内发送指令通过消除对确定和选择指定的通用寄存器或指定的备用通用寄存器的任何要求。

3. 发明授权

US5764942A Method and system for selective serialization of instruction processing in a superscalar processor system 失效
标题翻译：用于在超标量处理器系统中选择性地串行化指令处理的方法和系统
公开(公告)号：US5764942A
公开(公告)日：1998-06-09
申请号：US689437
申请日：1996-08-12
申请人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
发明人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
IPC分类号： G06F9/38 , G06F9/30 , G06F9/312
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855
摘要： The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the scalar instructions to a plurality of execution units on a nonsequential opportunistic basis. A group of scalar instructions fetched in an application specified ordered sequence on a nonsequential opportunistic basis is processed in the present invention. The present invention detects conditions requiring serialization during the processing. In response to a detection of a condition requiring serialization, processing of particular scalar instructions from the group of scalar instructions are selectively controlled, wherein at least a portion of the scalar instructions within the group of scalar instructions are thereafter processed in a serial fashion.
摘要翻译：本发明的方法和系统允许在能够提取应用指定的标量指令的有序序列的超标量处理器系统中增强指令调度效率，并且以非顺序的机会主义的方式在多个执行单元上同时分派一组标量指令。在本发明中处理以应用程序指定的顺序序列在非顺序机会性基础上提取的一组标量指令。本发明检测在处理期间需要串行化的条件。响应于需要串行化的条件的检测，选择性地控制来自标准指令组的特定标量指令的处理，其中标量指令组中的标量指令的至少一部分此后以串行方式被处理。

4. 发明授权

US08032849B2 Integrated circuit chip with modular design 失效
标题翻译：集成电路芯片采用模块化设计
公开(公告)号：US08032849B2
公开(公告)日：2011-10-04
申请号：US12130268
申请日：2008-05-30
申请人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
发明人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.
摘要翻译：公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

5. 发明授权

US07496776B2 Power throttling method and apparatus 失效
标题翻译：功率节流方法和装置
公开(公告)号：US07496776B2
公开(公告)日：2009-02-24
申请号：US10645024
申请日：2003-08-21
申请人： James Allan Kahle , David J. Shippy , Albert James Van Norstrand, Jr.
发明人： James Allan Kahle , David J. Shippy , Albert James Van Norstrand, Jr.
IPC分类号： G06F1/32
CPC分类号： G06F9/30112 , G06F1/3203 , G06F1/3287 , G06F9/30141 , G06F9/30189 , Y02D10/171 , Y02D50/20
摘要： Disclosed is an apparatus which deactivates both the AC as well as the DC component of power for various functions in a CPU. The CPU partitions dataflow registers and arithmetic units such that voltage can be removed from the upper portion of dataflow registers when the software is not utilizing same. Clock signals are also prevented from being applied to these non-utilized components. As an example, if a 64 bit CPU (processor unit) is to be used with both 32 and 64 bit software, the mentioned components may be partitioned in equal sized upper and lower portions. The logic signal for activating the removal of voltage may be obtained from a software-accessible architected control register designated as a machine state register in some CPUs. The same logic may be used in connection with removing voltage and clocks from other specialized functional components such as the floating point unit when software instructions do not presently require same.
摘要翻译：公开了一种对CPU中的各种功能的AC以及DC分量进行停用的装置。 CPU分配数据流寄存器和算术单元，使得当软件不使用相同时，可以从数据流寄存器的上部去除电压。还防止时钟信号被施加到这些未使用的组件。作为示例，如果要使用32位和64位软件的64位CPU（处理器单元），则所提到的组件可以被分成相同大小的上部和下部。用于激活电压去除的逻辑信号可以从在某些CPU中指定为机器状态寄存器的软件可访问的架构控制寄存器获得。当软件指令当前不需要相同时，相同的逻辑可用于从其他专门功能组件（例如浮点单元）中去除电压和时钟。

6. 发明授权

US07114035B2 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US07114035B2
公开(公告)日：2006-09-26
申请号：US10655365
申请日：2003-09-04
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

7. 发明授权

US07107363B2 Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation 失效
标题翻译：具有用于计算应用的带宽管理的微处理器和管理带宽分配的相关方法
公开(公告)号：US07107363B2
公开(公告)日：2006-09-12
申请号：US10464882
申请日：2003-06-19
申请人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Takeshi Yamazaki
发明人： Jeffrey Douglas Brown , Michael Norman Day , Charles Ray Johns , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F3/00
CPC分类号： G06F9/5011 , G06F2209/5014
摘要： The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing element and configured to shape storage requests for the processing of the application. In this embodiment, the microprocessor further includes bandwidth management circuitry coupled to the access shaper and configured to track the bandwidth usage based on the requests. A method of coordinating bandwidth allocation and a processor assembly are also disclosed.
摘要翻译：本发明在一个方面公开了一种微处理器。在一个实施例中，微处理器包括被配置为使用带宽来处理应用的处理元件。微处理器还包括一个接入整形器，它与处理元件相耦合，并配置成形成用于处理应用的存储请求。在该实施例中，微处理器还包括耦合到接入整形器的带宽管理电路，并且被配置为基于请求跟踪带宽使用。还公开了一种协调带宽分配的方法和处理器组件。

8. 发明授权

US07010626B2 DMA prefetch 失效
标题翻译： DMA预取
公开(公告)号：US07010626B2
公开(公告)日：2006-03-07
申请号：US11057454
申请日：2005-02-14
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.
摘要翻译：提供了一种用于将数据从系统存储器预取到计算机系统中用于直接存储器访问（DMA）机制的高速缓存的方法和装置。为处理器设置了DMA机制。检测到DMA机制的负载访问模式。基于负载访问模式预测至少一个潜在的数据负载。响应于该预测，在DMA命令请求数据之前，将数据从系统存储器预取到高速缓存。

9. 发明授权

US06779049B2 Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism 有权
标题翻译：具有附加处理单元的对称多处理系统能够访问共享存储器而不在结构上配置地址转换机制
公开(公告)号：US06779049B2
公开(公告)日：2004-08-17
申请号：US09736585
申请日：2000-12-14
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman , Masakazu Suzuoki , Takeshi Yamazaki
IPC分类号： G06F1328
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

10. 发明授权

US06697939B1 Basic block cache microprocessor with instruction history information 失效
标题翻译：具有指令历史信息的基本块缓存微处理器
公开(公告)号：US06697939B1
公开(公告)日：2004-02-24
申请号：US09477569
申请日：2000-01-06
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F900
CPC分类号： G06F9/3814 , G06F9/30174 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3861
摘要： A processor, data processing system, and a related method of execution are disclosed. The processor is suitable for receiving a set of instructions and organizing the set of instructions into an instruction group. The instruction group is then dispatched for execution. Upon executing the instruction group, instruction history information indicative of an exception event associated with the instruction group is recorded. Thereafter, the execution of the instruction is modified responsive to the instruction history information to prevent the exception event from occurring during a subsequent execution of the instruction group. The processor includes a storage facility such as an instruction cache, an L2 cache or a system memory, a cracking unit, and a basic block cache. The cracking unit is configured to receive a set of instructions from the storage facility. The cracking unit is adapted to organize the set of instructions into an instruction group.
摘要翻译：公开了一种处理器，数据处理系统和相关的执行方法。处理器适用于接收一组指令，并将该组指令组织到指令组中。然后调度指令组以执行。在执行指令组时，记录指示与指令组相关联的异常事件的指令历史信息。此后，响应于指令历史信息修改指令的执行，以防止在指令组的后续执行期间发生异常事件。处理器包括诸如指令高速缓存，L2高速缓存或系统存储器，破解单元和基本块高速缓存之类的存储设备。破裂单元被配置为从存储设施接收一组指令。裂解单元适于将该组指令组织成指令组。

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