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1. 发明授权

US07735072B1 Method and apparatus for profiling computer program execution 失效
标题翻译：用于分析计算机程序执行的方法和装置
公开(公告)号：US07735072B1
公开(公告)日：2010-06-08
申请号：US09637078
申请日：2000-08-11
申请人： Erik R. Altman , Kemal Ebcioglu , Michael Karl Gschwind , Sumedh Sathaye
发明人： Erik R. Altman , Kemal Ebcioglu , Michael Karl Gschwind , Sumedh Sathaye
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： According to a first aspect of the invention there is provided a method for profiling computer program executions in a computer processing system having a processor and a memory hierarchy. The method includes the step of executing a computer program. Profile counts are stored in a memory array for events associated with the execution of the computer program. The memory array is separate and distinct from the memory hierarchy so as to not perturb normal operations of the memory hierarchy.
摘要翻译：根据本发明的第一方面，提供了一种用于在具有处理器和存储器层次的计算机处理系统中对计算机程序执行进行分析的方法。该方法包括执行计算机程序的步骤。配置文件计数存储在与执行计算机程序相关的事件的存储器阵列中。存储器阵列与存储器层次结构是分开的，不同于内存层次结构的正常操作。

2. 发明授权

US07487330B2 Method and apparatus for transferring control in a computer system with dynamic compilation capability 失效
标题翻译：用于在具有动态编译能力的计算机系统中传送控制的方法和装置
公开(公告)号：US07487330B2
公开(公告)日：2009-02-03
申请号：US09847776
申请日：2001-05-02
申请人： Erik R. Altman , Kemal Ebcioglu , Michael Karl Gschwind , David Arnold Luick
发明人： Erik R. Altman , Kemal Ebcioglu , Michael Karl Gschwind , David Arnold Luick
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/45516
摘要： In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the instruction is disclosed. The system and method include the setting of a tag for entry points of each instruction in a first representation that has been translated to a second representation. The tag is stored in memory in association with each such instruction. When a given instruction in a first representation is to be executed, the tag is examined, and if it indicates that a translated version of the instruction has previously been generated, control is passed to execution of the instruction in the second representation. The second representation can be a different instruction set representation, or an optimized representation in the same instruction set as the original instruction.
摘要翻译：在动态编译计算机系统中，公开了一种用于将控制从第一表示中的指令的执行有效地传送到指令的第二表示的系统和方法。该系统和方法包括在已被翻译为第二表示的第一表示中设置每个指令的入口点的标签。标签与每个这样的指令相关联地存储在存储器中。当要执行第一表示中的给定指令时，检查标签，并且如果其指示已经生成了指令的转换版本，则将控制传递给第二表示中的指令的执行。第二表示可以是与原始指令相同的指令集中的不同指令集表示或优化表示。

3. 发明授权

US07461209B2 Transient cache storage with discard function for disposable data 有权
标题翻译：用于一次性数据的具有丢弃功能的瞬态缓存存储
公开(公告)号：US07461209B2
公开(公告)日：2008-12-02
申请号：US11295300
申请日：2005-12-06
申请人： Erik R. Altman , Michael Karl Gschwind , Robert Kevin Montoye , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik R. Altman , Michael Karl Gschwind , Robert Kevin Montoye , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F12/12
CPC分类号： G06F12/1491 , G06F9/3808 , G06F9/3844 , G06F12/0802 , G06F12/0804 , G06F12/12
摘要： A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.
摘要翻译：公开了一种用于存储非关键处理器信息而不对处理器设计造成重大成本的方法和装置。瞬态数据存储在处理器本地缓存层次结构中。附加控制位构成高速缓存地址的一部分，其中具有控制位置位的地址被指定为“瞬时存储地址”。瞬态存储地址不会被写回外部主存储器，而当从最后一级高速缓存驱逐时，它们将被丢弃。优选地，瞬态存储地址是“特权的”，因为它们不能被软件访问或只能具有具有适当权限的监督或管理员级软件访问。提供了许多管理功能/指令，以允许管理员/管理软件管理和/或修改瞬态缓存存储的行为。这种瞬态存储方案允许高速缓存层级来存储处理器核心可能使用的数据项，但是可能太昂贵以分配给外部存储器。

4. 发明授权

US06907477B2 Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors 失效
标题翻译：使用DMAC的对称多处理系统允许连接的处理器进行地址转换
公开(公告)号：US06907477B2
公开(公告)日：2005-06-14
申请号：US10782044
申请日：2004-02-19
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
IPC分类号： G06F12/10 , G06F13/28 , G06F9/28 , G06F13/368
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：一种用于附接处理单元访问SMT系统中的共享存储器的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

5. 发明授权

US07979682B2 Method and system for preventing livelock due to competing updates of prediction information 有权
标题翻译：由于预测信息的竞争更新而防止活动锁定的方法和系统
公开(公告)号：US07979682B2
公开(公告)日：2011-07-12
申请号：US12051322
申请日：2008-03-19
申请人： Erik R. Altman , Vijayalakshmi Srinivasan
发明人： Erik R. Altman , Vijayalakshmi Srinivasan
IPC分类号： G06F9/30
CPC分类号： G06F9/528 , G06F9/30043 , G06F9/3842 , G06F9/3861
摘要： A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is mispredicted to form an appended instruction. A prediction override bit is set on the appended instruction. Then, the appended instruction is executed with the real event outcome.
摘要翻译：防止活动锁的系统。预测事件的结果将形成事件结果预测。将事件结果预测与要访问的基准的正确值进行比较。当事件的结果被错误预测以形成附加的指令时，指令将附加真实的事件结果。在附加的指令上设置预测覆盖位。然后，附加的指令与实际事件结果一起执行。

6. 发明授权

US07865699B2 Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code 有权
标题翻译：以与现有代码兼容的方式扩展具有固定长度指令的处理器中指令位数目的方法和装置
公开(公告)号：US07865699B2
公开(公告)日：2011-01-04
申请号：US11931815
申请日：2007-10-31
申请人： Erik R Altman , Michael Gschwind , David A. Luick , Daniel A. Prener , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman
发明人： Erik R Altman , Michael Gschwind , David A. Luick , Daniel A. Prener , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman
IPC分类号： G06F9/00
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/30181 , G06F9/30185
摘要： This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.
摘要翻译：本发明涉及存储在计算机可读介质上的装置，方法和计算机程序。计算机程序包括与具有代码页的指令单元一起使用的指令，并且具有用于将代码页划分为至少两个部分的计算机程序代码，用于在其第一部分中存储多个指令字，并且至少与一个指令字，用于在其第二部分中存储对第一部分中的每个指令字的扩展。计算机程序还包括用于设置至少一个页表条目位的状态的计算机程序代码，用于通过代码页在代码页上指示代码页是否被分割成用于存储指令字的第一和第二部分，以及它们扩展，还是包含代码页而不是仅存储指令字的单个部分。

7. 发明授权

US07516310B2 Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor 失效
标题翻译：通过存储指令在多线程处理器中搜索减少飞行载荷次数的方法
公开(公告)号：US07516310B2
公开(公告)日：2009-04-07
申请号：US11422996
申请日：2006-06-08
申请人： Erik R. Altman , Vijayalakshmi Srinivasan
发明人： Erik R. Altman , Vijayalakshmi Srinivasan
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/3834 , G06F12/0842 , Y02D10/13
摘要： A method for reducing the number of times in-flight loads must be searched by store instructions in a multi-threaded processor. A load issue for a thread t_old is frozen for a number of cycles. A t13 new load instruction is rejected. A notification is sent to the rest of the processor that the t_new load instruction has been rejected. A load reorder queue (LRQ) of a t_old is snooped for any load which comes from a cache line L accessed by the load instruction and then forces such loads to be re-executed. Ownership of line L is changed to thread t_new.
摘要翻译：必须通过存储指令在多线程处理器中搜索减少飞行载荷次数的方法。线程t_old的加载问题会冻结多个周期。 t13新加载指令被拒绝。发送处理器的其余部分通知t_new加载指令已被拒绝。对于来自由加载指令访问的高速缓存行L的任何负载，并监视t_old的加载重新排序队列（LRQ），然后强制重新执行此类负载。线L的所有权更改为线程t_new。

8. 发明授权

US07340588B2 Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code 有权
标题翻译：以与现有代码兼容的方式扩展具有固定长度指令的处理器中的指令位数
公开(公告)号：US07340588B2
公开(公告)日：2008-03-04
申请号：US10720585
申请日：2003-11-24
申请人： Erik R Altman , Michael Gschwind , David A. Luick , Daniel A. Prener , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman
发明人： Erik R Altman , Michael Gschwind , David A. Luick , Daniel A. Prener , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman
IPC分类号： G06F12/02
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/30181 , G06F9/30185
摘要： This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.
摘要翻译：本发明涉及存储在计算机可读介质上的装置，方法和计算机程序。计算机程序包括与具有代码页的指令单元一起使用的指令，并且具有用于将代码页划分为至少两个部分的计算机程序代码，用于在其第一部分中存储多个指令字，并且至少与一个指令字，用于在其第二部分中存储对第一部分中的每个指令字的扩展。计算机程序还包括用于设置至少一个页表条目位的状态的计算机程序代码，用于通过代码页在代码页上指示代码页是否被分割成用于存储指令字的第一和第二部分，以及它们扩展，还是包含代码页而不是仅存储指令字的单个部分。

9. 发明申请

US20080010441A1 MEANS FOR SUPPORTING AND TRACKING A LARGE NUMBER OF IN-FLIGHT LOADS IN AN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：用于支持和跟踪在订单处理器中的大量航空货运的手段
公开(公告)号：US20080010441A1
公开(公告)日：2008-01-10
申请号：US11428589
申请日：2006-07-05
申请人： Erik R. Altman , Vijayalakshmi Srinivasan
发明人： Erik R. Altman , Vijayalakshmi Srinivasan
IPC分类号： G06F9/44
CPC分类号： G06F9/44
摘要： A method for supporting and tracking a plurality of loads in an out-of-order processor being run by a program includes executing instructions on the processor, the instructions including an address from which data is to be loaded and memory locations from which load data is received, determining inputs of the instructions, determining a function unit on which to execute the instructions, storing the plurality of instructions in both a LRQ and a LIP queue, the LRQ comprising a list of the plurality of stores and the LIP comprising a list of respective addresses of the plurality of loads, dividing the LIP into a set of congruence classes, each holding a predetermined number of the loads, allowing the loads to be stored in the memory locations, snooping the load data, and allowing a plurality of snoops to selectively invalidate the load data from snooped addresses so as to maintain sequential load consistency.
摘要翻译：一种用于支持和跟踪由程序运行的无序处理器中的多个负载的方法包括在处理器上执行指令，指令包括要从中加载数据的地址和加载数据所在的存储位置接收，确定所述指令的输入，确定执行所述指令的功能单元，将所述多个指令存储在LRQ和LIP队列中，所述LRQ包括所述多个存储的列表，并且所述LIP包括：多个负载的相应地址，将该LIP划分为一组一致的等级，每个等级保持预定数量的负载，允许将负载存储在存储器位置中，窥探负载数据，并允许多个监视有选择地使来自探测地址的负载数据无效，以保持顺序的负载一致性。

10. 发明申请

US20080010440A1 MEANS FOR SUPPORTING AND TRACKING A LARGE NUMBER OF IN-FLIGHT STORES IN AN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：用于支持和跟踪在订单处理程序中的大量飞行存储
公开(公告)号：US20080010440A1
公开(公告)日：2008-01-10
申请号：US11428582
申请日：2006-07-05
申请人： Erik R. Altman , Vijayalakshmi Srinivasan
发明人： Erik R. Altman , Vijayalakshmi Srinivasan
IPC分类号： G06F9/44
CPC分类号： G06F9/44
摘要： A method for supporting and tracking a plurality of stores in an out-of-order processor run by a predetermined program includes executing a plurality of instructions on the processor, each instruction including an address from which data is to be loaded and a plurality of memory locations from which load data is received, determining inputs of the instructions, determining a function unit on which to execute the instructions; storing the plurality of instructions in both a Retirement Store Queue (RSTQ) and a Forwarding Store Queue (FSTQ), the RSTQ comprising a list of the plurality of stores and the FSTQ comprising a list of respective addresses of the plurality of stores, allowing the plurality of stores to be stored in the plurality of memory locations, and allowing the plurality of stores to forward the load data only after the instructions have determined that the predetermined number of the stores has completed the series of the execution processes.
摘要翻译：一种用于在由预定程序运行的无序处理器中支持和跟踪多个存储的方法包括在处理器上执行多个指令，每个指令包括要从其加载数据的地址和多个存储器接收负载数据的位置，确定指令的输入，确定执行指令的功能单元; 将所述多个指令存储在退休存储队列（RSTQ）和转发存储队列（FSTQ）两者中，所述RSTQ包括所述多个存储的列表，并且所述FSTQ包括所述多个存储的相应地址的列表，要存储在多个存储单元中的多个存储器，并且只有在指令已经确定预定数量的存储器已经完成了一系列执行处理之后才允许多个存储器转发加载数据。

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