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1. 发明授权

US5898882A Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage 失效
标题翻译：利用独立访问的中间存储器在超标量处理器系统中增强指令调度的方法和系统
公开(公告)号：US5898882A
公开(公告)日：1999-04-27
申请号：US1865
申请日：1993-01-08
申请人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
发明人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
IPC分类号： G06F9/38 , G06F15/16
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855
摘要： A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
摘要翻译：一种用于在超标量处理器系统中允许单周期指令调度的方法和系统，其将多个指令同时分配到一组执行单元以执行并将其结果放置在指定的通用寄存器内。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，允许在单个周期内发送指令通过消除对确定和选择指定的通用寄存器或指定的备用通用寄存器的任何要求。

2. 发明授权

US5764942A Method and system for selective serialization of instruction processing in a superscalar processor system 失效
标题翻译：用于在超标量处理器系统中选择性地串行化指令处理的方法和系统
公开(公告)号：US5764942A
公开(公告)日：1998-06-09
申请号：US689437
申请日：1996-08-12
申请人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
发明人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
IPC分类号： G06F9/38 , G06F9/30 , G06F9/312
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855
摘要： The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the scalar instructions to a plurality of execution units on a nonsequential opportunistic basis. A group of scalar instructions fetched in an application specified ordered sequence on a nonsequential opportunistic basis is processed in the present invention. The present invention detects conditions requiring serialization during the processing. In response to a detection of a condition requiring serialization, processing of particular scalar instructions from the group of scalar instructions are selectively controlled, wherein at least a portion of the scalar instructions within the group of scalar instructions are thereafter processed in a serial fashion.
摘要翻译：本发明的方法和系统允许在能够提取应用指定的标量指令的有序序列的超标量处理器系统中增强指令调度效率，并且以非顺序的机会主义的方式在多个执行单元上同时分派一组标量指令。在本发明中处理以应用程序指定的顺序序列在非顺序机会性基础上提取的一组标量指令。本发明检测在处理期间需要串行化的条件。响应于需要串行化的条件的检测，选择性地控制来自标准指令组的特定标量指令的处理，其中标量指令组中的标量指令的至少一部分此后以串行方式被处理。

3. 发明授权

US5978896A Method and system for increased instruction dispatch efficiency in a superscalar processor system 失效
标题翻译：用于在超标量处理器系统中提高指令调度效率的方法和系统
公开(公告)号：US5978896A
公开(公告)日：1999-11-02
申请号：US289801
申请日：1994-08-12
申请人： James Allan Kahle , Chin-Cheng Kau , David Steven Levitan , Aubrey Deene Ogden
发明人： James Allan Kahle , Chin-Cheng Kau , David Steven Levitan , Aubrey Deene Ogden
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3885
摘要： A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.
摘要翻译：一种用于在具有指令队列的超标量处理器系统中提高指令调度效率的方法和系统，所述指令队列用于以应用指定的顺序顺序接收一组指令，以及指令调度单元，用于将指令从相关联的指令缓冲器分派到多个执行单元，基础。周期性地确定关联指令缓冲器内的指令的调度状态，并且响应于在指令缓冲器的开始处的指令的调度，剩余的指令在应用指定的顺序顺序的指令缓冲器内移动，部分组的指令通过选择性控制的多路复用电路从指令队列加载到指令缓冲器中。以这种方式，可以将附加指令分派到可用的执行单元，而不需要完全调度先前的指令组。

4. 发明授权

US5732005A Single-precision, floating-point register array for floating-point units performing double-precision operations by emulation 失效
标题翻译：用于通过仿真执行双精度操作的浮点单元的单精度浮点寄存器阵列
公开(公告)号：US5732005A
公开(公告)日：1998-03-24
申请号：US386980
申请日：1995-02-10
申请人： James Allan Kahle , Tai Dinh Ngo , Aubrey Deene Ogden , Michael Putrino , Johm Victor Sell
发明人： James Allan Kahle , Tai Dinh Ngo , Aubrey Deene Ogden , Michael Putrino , Johm Victor Sell
IPC分类号： G06F7/57 , G06F7/00 , G06F7/38
CPC分类号： G06F7/483 , G06F2207/382
摘要： A single-precision floating-point register array for a floating-point execution unit that performs double-precision operations by emulation is provided. The register array comprises a plurality of single-precision floating-point registers and a storage device that stores one or more status bits in association with each of the plurality of registers; the status bits associated with each register indicate either that the associated data register contains single-precision or integer data, or that the data for the associated register is contained in an emulated register in memory that is mapped to the associated register. When a register is a source for an operation, the status bits associated with the register are checked and the required operand data for that register is read from the register or from an emulated register mapped to that register, as a function of the state of the status bits.
摘要翻译：提供了一种用于通过仿真执行双精度操作的浮点执行单元的单精度浮点寄存器阵列。寄存器阵列包括多个单精度浮点寄存器和与多个寄存器中的每一个相关联地存储一个或多个状态位的存储器件; 与每个寄存器相关联的状态位指示相关联的数据寄存器包含单精度或整数数据，或者相关联寄存器的数据包含在映射到相关寄存器的存储器中的仿真寄存器中。当寄存器是操作的源时，检查与寄存器相关联的状态位，并且从寄存器或映射到该寄存器的仿真寄存器读取该寄存器所需的操作数数据，作为该寄存器状态的函数状态位。

5. 发明授权

US5758141A Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register 失效
标题翻译：在利用机器状态寄存器内的特殊访问位的超标量处理器系统内选择性地支持非架构指令的方法和系统
公开(公告)号：US5758141A
公开(公告)日：1998-05-26
申请号：US386977
申请日：1995-02-10
申请人： James Allan Kahle , Albert J. Loper , Soummya Mallick , Aubrey Deene Ogden , John Victor Sell
发明人： James Allan Kahle , Albert J. Loper , Soummya Mallick , Aubrey Deene Ogden , John Victor Sell
IPC分类号： G06F9/30 , G06F9/318 , G06F9/455
CPC分类号： G06F9/30181 , G06F9/30145 , G06F9/30189 , G06F9/45554
摘要： A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.
摘要翻译：一种用于允许在超标量处理器系统内选择性地支持非架构指令的方法和系统。系统机器状态寄存器内的特殊访问位被提供和设置为响应于期望执行非架构指令的应用程序的每个启动。此后，每当非架构化指令被解码时，确定特殊访问位的状态。响应于特殊访问位的设置状态执行非架构指令。如果未设置特殊访问位，则响应于非架构化指令的尝试执行而发出非法指令程序中断。以这种方式，例如，复杂指令集计算（CISC）指令可以选择性地启用以在精简指令集计算（RISC）数据处理系统中执行，同时保持与精简指令集计算（RISC）指令的完全架构符合性。

6. 发明授权

US5764969A Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization 失效
标题翻译：利用混合用户级别和部分概念同步的监督级别指令来增强管理操作的方法和系统
公开(公告)号：US5764969A
公开(公告)日：1998-06-09
申请号：US387149
申请日：1995-02-10
申请人： James Allan Kahle , Albert J. Loper , Soummya Mallick , Aubrey Deene Ogden , John Victor Sell
发明人： James Allan Kahle , Albert J. Loper , Soummya Mallick , Aubrey Deene Ogden , John Victor Sell
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48 , G06F12/14 , G06F9/44
CPC分类号： G06F9/461 , G06F12/1475
摘要： A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to "supervisor;" external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed. A disable special access (DSA) instruction is then executed which restores the bits within the machine state register which were modified during the ESA instruction. The ESA and DSA instructions are implemented without modifying the instruction stream by utilizing user level procedure calls, thereby reducing the overhead of the branch table necessary to determine the desired execution path.
摘要翻译：一种用于在超标量数据处理系统中增强系统管理操作的方法和系统。在受保护的存储器空间内执行所选特权操作的这些监督级指令首先被识别为不需要完整的上下文同步。每次执行这样的指令时，执行使能特殊访问（ESA）指令作为该指令或指令组的入口点。存储用于数据处理系统的机器状态寄存器的一部分，然后如下修改机器状态寄存器：设置问题位，将执行特权状态改变为“主管”; 外部中断被禁用; 并设置访问权限状态位; 并设置特殊访问模式位，允许执行特殊指令。然后执行在受保护的存储器空间内执行所选择的特权操作的指令。然后执行禁用特殊访问（DSA）指令，其恢复机器状态寄存器中在ESA指令期间被修改的位。通过利用用户级过程调用来实现ESA和DSA指令而不修改指令流，从而减少确定所需执行路径所需的分支表的开销。

7. 发明授权

US5715420A Method and system for efficient memory management in a data processing system utilizing a dual mode translation lookaside buffer 失效
标题翻译：在利用双模式翻转后备缓冲器的数据处理系统中有效的存储器管理的方法和系统
公开(公告)号：US5715420A
公开(公告)日：1998-02-03
申请号：US387147
申请日：1995-02-10
申请人： James Allan Kahle , Albert J. Loper , Aubrey Deene Ogden , John Victor Sell , Gregory L. Limes
发明人： James Allan Kahle , Albert J. Loper , Aubrey Deene Ogden , John Victor Sell , Gregory L. Limes
IPC分类号： G06F12/10 , G06F12/14 , G06F21/02 , G06F12/00
CPC分类号： G06F12/145 , G06F12/1027
摘要： A method and system for efficient memory management in a data processing system which utilizes a memory management unit to translate effective addresses into real addresses within a translation lookaside buffer is disclosed. During a first mode of operation a selected number of effective address identifiers are stored in the translation lookaside buffer. In association with each virtual address identifier is a corresponding real address entry for a single memory block wherein selected virtual addresses may be translated into corresponding real addresses utilizing the translation lookaside buffer. In a second mode of operation, a selected number of virtual address identifiers are stored in a translation lookaside buffer and each virtual address identifier has a number of protection bits stored in association therewith, wherein each protection bit is indicative of a protection status for a large number of contiguous memory blocks beginning with the associated virtual address identifier, wherein memory block protection may be provided for a large number of memory blocks utilizing a fixed size translation lookaside buffer.
摘要翻译：公开了一种在数据处理系统中有效地进行存储器管理的方法和系统，其利用存储器管理单元将有效地址转换为翻译后备缓冲器内的实际地址。在第一操作模式期间，选择数量的有效地址标识符被存储在转换后备缓冲器中。与每个虚拟地址标识符相关联的是用于单个存储器块的对应的实际地址条目，其中所选择的虚拟地址可以使用转换后备缓冲器被转换成相应的实际地址。在第二操作模式中，选择数量的虚拟地址标识符被存储在转换后备缓冲器中，并且每个虚拟地址标识符具有与其相关联地存储的多个保护位，其中每个保护位指示大的保护位的保护状态以相关联的虚拟地址标识符开始的连续存储器块的数量，其中可以使用固定尺寸的转换后备缓冲器为大量存储器块提供存储块保护。

8. 发明授权

US06209081B1 Method and system for nonsequential instruction dispatch and execution in a superscalar processor system 失效
标题翻译：在超标量处理器系统中用于非顺序指令调度和执行的方法和系统
公开(公告)号：US06209081B1
公开(公告)日：2001-03-27
申请号：US08255130
申请日：1994-06-07
申请人： James Allan Kahle , Donald Emil Waldecker
发明人： James Allan Kahle , Donald Emil Waldecker
IPC分类号： G06F1500
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/384 , G06F9/3861 , G06F9/3863
摘要： A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer. An indication of the status of each instruction is maintained within a completion buffer and thereafter utilized to selectively transfer results within the intermediate storage buffers to selected general purpose registers in an order consistent with an application specified sequential order. The occurrence of an interrupt which prohibits completion of a selected instruction can therefore be accurately identified within the completion buffer.
摘要翻译：一种用于在超标量处理器系统中允许非顺序指令调度的方法和系统，其在机会性的基础上将顺序排列的多个指令同时分派到一组执行单元，以便在指定的通用寄存器内执行和将其结果放置。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用的执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，从而允许执行每个指令的结果存储在中间存储缓冲区中。每个指令的状态的指示保持在完成缓冲器内，然后用于以与应用指定的顺序顺序一致的顺序将中间存储缓冲器内的结果选择性地传送到所选通用寄存器。因此，可以在完成缓冲器内准确地识别出禁止完成所选指令的中断的发生。

9. 发明授权

US5761473A Method and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing partial data dependency interlocking 失效
标题翻译：使用部分数据依赖互锁的超标量过程系统中提高指令同步效率的方法和系统
公开(公告)号：US5761473A
公开(公告)日：1998-06-02
申请号：US1863
申请日：1993-01-08
申请人： James Allan Kahle , Chin-Cheng Kau
发明人： James Allan Kahle , Chin-Cheng Kau
IPC分类号： G06F9/38 , G06F9/345
CPC分类号： G06F9/3838
摘要： A method and system for increased instruction synchronization efficiency in a superscalar processor system which includes instructions having multiple source and destination operands. Simultaneous dispatching of multiple instructions creates a source-to-destination data dependency problem in that the results of one instruction may be necessary to accomplish execution of a second instruction. Data dependency hazards may be eliminated by prohibiting each instruction from dispatching until all possible data dependencies have been eliminated by the completion of preceding instructions; however, instruction dispatch efficiency is substantially decreased utilizing this technique. Data dependency interlock circuitry may be utilized to clear possible data dependency hazards; however, the complexity of such circuitry increases dramatically as the number of interlocked sources and destinations increases. The method and system of the present invention utilizes data dependency interlock circuitry capable of interlocking two source operands by two destination operands for each instruction. Instructions having three or more source operands are interlocked at the dispatch stage for the first two source operands utilizing existing data dependency interlock circuitry. Thereafter, the instruction is dispatched only after data dependency hazards are cleared for the first two source operands, utilizing the data dependency interlock circuitry, and all instructions preceding the instruction have been completed, eliminating possible data dependency hazards for the third source operand. In this manner, instructions which include three source operands may be synchronized without requiring a substantial increase in data dependency interlock circuitry and with only a slight degradation in system efficiency.
摘要翻译：一种用于在包括具有多个源和目的地操作数的指令的超标量处理器系统中提高指令同步效率的方法和系统。多个指令的同时调度会产生源对目标数据依赖性问题，因为一个指令的结果可能需要完成第二个指令的执行。可以通过禁止每个指令进行调度直到所有可能的数据相关性已经通过完成前面的指令而被消除来消除数据依赖危害; 然而，利用这种技术，指令调度效率显着降低。可以利用数据依赖互锁电路来清除可能的数据依赖危害; 然而，随着互锁源和目的地的数量的增加，这种电路的复杂性急剧增加。本发明的方法和系统利用数据相关互锁电路，其能够通过用于每个指令的两个目的地操作数来互锁两个源操作数。具有三个或更多个源操作数的指令在使用现有数据依赖性互锁电路的前两个源操作数的调度阶段互锁。此后，只有在前两个源操作数的数据依赖性危险被清除之后，才使用数据相关联锁电路来调度指令，并且完成了指令之前的所有指令，从而消除了对第三源操作数的可能的数据依赖性危害。以这种方式，包括三个源操作数的指令可以被同步，而不需要数据依赖性联锁电路的显着增加，并且只有系统效率的轻微降低。

10. 发明授权

US08032849B2 Integrated circuit chip with modular design 失效
标题翻译：集成电路芯片采用模块化设计
公开(公告)号：US08032849B2
公开(公告)日：2011-10-04
申请号：US12130268
申请日：2008-05-30
申请人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
发明人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.
摘要翻译：公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

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