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1. 发明申请

US20070011562A1 Mitigating silent data corruption in a buffered memory module architecture 失效
标题翻译：减轻缓冲内存模块架构中的无声数据损坏
公开(公告)号：US20070011562A1
公开(公告)日：2007-01-11
申请号：US11165693
申请日：2005-06-24
申请人： James Alexander , Suresh Chittor , Dennis Brzezinski , Kai Cheng
发明人： James Alexander , Suresh Chittor , Dennis Brzezinski , Kai Cheng
IPC分类号： H03M13/00
CPC分类号： G06F11/1004 , H03M13/09 , H03M13/19
摘要： Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于减轻完全缓冲存储器模块架构中的无声数据损坏的系统，装置和方法。在一个实施例中，存储器控制器包括具有M位CRC和N位CRC的存储器通道位通道误差检测器，其中N小于M.如果至少一个位线内存通道失败。在一个实施例中，如果至少一个位通道已经失败，则存储器控制器选择性地将纠错码（ECC）的强错误检测能力与N位CRC结合起来，以指示重新发送故障数据的需要。描述和要求保护其他实施例。

2. 发明申请

US20070089035A1 Silent data corruption mitigation using error correction code with embedded signaling fault detection 有权
标题翻译：使用具有嵌入式信令故障检测的纠错码进行静音数据损坏缓解
公开(公告)号：US20070089035A1
公开(公告)日：2007-04-19
申请号：US11240111
申请日：2005-09-30
申请人： James Alexander , Suresh Chittor , Dennis Brzezinski , Kai Cheng , Henk Neefs
发明人： James Alexander , Suresh Chittor , Dennis Brzezinski , Kai Cheng , Henk Neefs
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G06F11/1008 , G11C5/04 , G11C29/022 , G11C2029/0411
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.
摘要翻译：本发明的实施例一般涉及使用具有嵌入式信令故障检测的纠错码来减轻无声数据损坏的系统，方法和装置。在一个实施例中，存储器控制器包括扩展纠错码（ECC）和链路信令故障检测逻辑。扩展ECC包括嵌入式信令故障检测。在一个实施例中，扩展ECC增强了信令故障检测逻辑的信令故障检测能力。

3. 发明授权

US07734980B2 Mitigating silent data corruption in a buffered memory module architecture 失效
标题翻译：减轻缓冲内存模块架构中的无声数据损坏
公开(公告)号：US07734980B2
公开(公告)日：2010-06-08
申请号：US11165693
申请日：2005-06-24
申请人： James W. Alexander , Suresh Chittor , Dennis W. Brzezinski , Kai Cheng , Rajat Agarwal
发明人： James W. Alexander , Suresh Chittor , Dennis W. Brzezinski , Kai Cheng , Rajat Agarwal
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1004 , H03M13/09 , H03M13/19
摘要： Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于减轻完全缓冲存储器模块架构中的无声数据损坏的系统，装置和方法。在一个实施例中，存储器控制器包括具有M位CRC和N位CRC的存储器通道位通道误差检测器，其中N小于M.如果至少一个位线内存通道失败。在一个实施例中，如果至少一个位通道已经失败，则存储器控制器选择性地将纠错码（ECC）的强错误检测能力与N位CRC结合起来，以指示重新发送故障数据的需要。描述和要求保护其他实施例。

4. 发明授权

US07644347B2 Silent data corruption mitigation using error correction code with embedded signaling fault detection 有权
标题翻译：使用具有嵌入式信令故障检测的纠错码进行静音数据损坏缓解
公开(公告)号：US07644347B2
公开(公告)日：2010-01-05
申请号：US11240111
申请日：2005-09-30
申请人： James W. Alexander , Suresh Chittor , Dennis W. Brzezinski , Kai Cheng , Henk Neefs , Rajat Agarwal
发明人： James W. Alexander , Suresh Chittor , Dennis W. Brzezinski , Kai Cheng , Henk Neefs , Rajat Agarwal
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G06F11/1008 , G11C5/04 , G11C29/022 , G11C2029/0411
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.
摘要翻译：本发明的实施例一般涉及使用具有嵌入式信令故障检测的纠错码来减轻无声数据损坏的系统，方法和装置。在一个实施例中，存储器控制器包括扩展纠错码（ECC）和链路信令故障检测逻辑。扩展ECC包括嵌入式信令故障检测。在一个实施例中，扩展ECC增强了信令故障检测逻辑的信令故障检测能力。

5. 发明申请

US20070150672A1 Fully buffered DIMM read data substitution for write acknowledgement 失效
标题翻译：全缓冲DIMM读取数据替代写入确认
公开(公告)号：US20070150672A1
公开(公告)日：2007-06-28
申请号：US11321322
申请日：2005-12-28
申请人： James Alexander , Rajat Agarwal , Bruce Christenson , Kai Cheng
发明人： James Alexander , Rajat Agarwal , Bruce Christenson , Kai Cheng
IPC分类号： G06F13/00
CPC分类号： G06F13/4234 , G06F13/1673
摘要： A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.
摘要翻译：内存控制器使用一种方案来从重放队列中退出两个条目，这是由于单个无错误的响应。有利地，重放队列中的条目可以比常规系统更早地退出，从而最小化重播队列的大小。

6. 发明授权

US09862601B2 Plasmonic force manipulation in nanostructures 有权
公开(公告)号：US09862601B2
公开(公告)日：2018-01-09
申请号：US13518570
申请日：2010-12-24
申请人： Chang Chen , Pol Van Dorpe , Kai Cheng , Tim Stakenborg , Liesbet Lagae
发明人： Chang Chen , Pol Van Dorpe , Kai Cheng , Tim Stakenborg , Liesbet Lagae
IPC分类号： B82Y15/00 , G01N21/65 , C12Q1/68 , G01N33/487 , G01N33/538
CPC分类号： B82Y15/00 , C12Q1/6869 , G01N33/48721 , G01N33/538 , Y10T436/143333 , C12Q2565/631 , C12Q2565/607
摘要： A system (100) is described for characterizing and/or manipulating molecules. The system may especially be suitable for biological molecules, although the invention is not limited thereto. The system (100) comprises a substrate (110) comprising a nanostructure (120) being suitable for translocation of molecules through the nanostructure (120). It furthermore comprises a means (210) for translocating molecules through the nanostructure (120) and a plasmonic force field generating means (130) adapted for influencing the translocation speed of the particle by applying a plasmonic force field at the nanostructure (120). A corresponding method also is described.

7. 发明授权

US08745306B2 Scalable distributed memory and I/O multiprocessor system 有权
标题翻译：可扩展分布式内存和I / O多处理器系统
公开(公告)号：US08745306B2
公开(公告)日：2014-06-03
申请号：US13590936
申请日：2012-08-21
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

8. 发明授权

US08623685B2 Method of manufacturing a light emitting diode 有权
标题翻译：制造发光二极管的方法
公开(公告)号：US08623685B2
公开(公告)日：2014-01-07
申请号：US13092854
申请日：2011-04-22
申请人： Kai Cheng
发明人： Kai Cheng
IPC分类号： H01L33/00
CPC分类号： H01L33/007 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L33/0079 , H01L33/12 , H01L33/20 , H01L2933/0083
摘要： A method of manufacturing a light emitting diode is disclosed. In one aspect, the light emitting diode has a carrier, an active layer structure of III-nitride type materials, and a photonic crystal structure of III-nitride type materials. The active layer structure includes a first active layer with an n-type doped layer and a p-type doped layer and suitably a quantum well structure. The photonic crystal structure includes periodically distributed trenches or periodically distributed pillars spaced by one or more trenches. The photonic crystal structure includes an overgrowth layer within which a diameter of a trench gradually increases, and a directional photonic crystal layer in which the diameter of a trench is substantially constant. The diode may be formed in a method wherein the directional photonic crystal layer is provided on a three-dimensional pattern that exposes selected areas of the first surface of the substrate.
摘要翻译：公开了一种制造发光二极管的方法。一方面，发光二极管具有载流子，III族氮化物型材料的有源层结构和III族氮化物型材料的光子晶体结构。有源层结构包括具有n型掺杂层和p型掺杂层的第一有源层，并且适当地为量子阱结构。光子晶体结构包括由一个或多个沟槽隔开的周期性分布的沟槽或周期性分布的柱。光子晶体结构包括其中沟槽直径逐渐增加的过度生长层，以及沟槽直径基本上恒定的定向光子晶体层。二极管可以以一种方法形成，其中定向光子晶体层设置在暴露基板的第一表面的选定区域的三维图案上。

9. 发明授权

US08437001B2 Method for forming a nanostructure penetrating a layer 有权
标题翻译：形成穿透层的纳米结构的方法
公开(公告)号：US08437001B2
公开(公告)日：2013-05-07
申请号：US13157154
申请日：2011-06-09
申请人： Kai Cheng , Pol Van Dorpe , Liesbet Lagae , Gustaaf Borghs , Chang Chen
发明人： Kai Cheng , Pol Van Dorpe , Liesbet Lagae , Gustaaf Borghs , Chang Chen
IPC分类号： G01N21/00
CPC分类号： B82Y15/00 , B82Y20/00 , B82Y40/00 , G01N21/554 , G01N21/648 , G01N21/658 , G01N33/48721 , G01N2021/653 , Y10S977/724 , Y10S977/924
摘要： A method for forming a nanostructure penetrating a layer and the device made thereof is disclosed. In one aspect, the device has a substrate, a layer present thereon, and a nanostructure penetrating the layer. The nanostructure defines a nanoscale passageway through which a molecule to be analyzed can pass through. The nanostructure has, in cross-sectional view, a substantially triangular shape. This shape is particularly achieved by growth of an epitaxial layer having crystal facets defining tilted sidewalls of the nanostructure. It is highly suitably for use for optical characterization of molecular structure, particularly with surface plasmon enhanced transmission spectroscopy.
摘要翻译：公开了一种形成穿透层的纳米结构的方法及其制造的器件。在一个方面，该装置具有基底，存在于其上的层和穿透该层的纳米结构。纳米结构定义了一个纳米尺度的通道，待分析的分子通过该通道通过。纳米结构在横截面图中具有基本上三角形的形状。通过具有限定纳米结构的倾斜侧壁的晶面的外延层的生长，特别地实现了这种形状。它非常适合用于分子结构的光学表征，特别是用于表面等离子体增强透射光谱。

10. 发明申请

US20110260211A1 METHOD OF MANUFACTURING A LIGHT EMITTING DIODE 有权
标题翻译：制造发光二极管的方法
公开(公告)号：US20110260211A1
公开(公告)日：2011-10-27
申请号：US13092854
申请日：2011-04-22
申请人： Kai Cheng
发明人： Kai Cheng
IPC分类号： H01L33/02
CPC分类号： H01L33/007 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L33/0079 , H01L33/12 , H01L33/20 , H01L2933/0083
摘要： A method of manufacturing a light emitting diode is disclosed. In one aspect, the light emitting diode has a carrier, an active layer structure of III-nitride type materials, and a photonic crystal structure of III-nitride type materials. The active layer structure includes a first active layer with an n-type doped layer and a p-type doped layer and suitably a quantum well structure. The photonic crystal structure includes periodically distributed trenches or periodically distributed pillars spaced by one or more trenches. The photonic crystal structure includes an overgrowth layer within which a diameter of a trench gradually increases, and a directional photonic crystal layer in which the diameter of a trench is substantially constant. The diode may be formed in a method wherein the directional photonic crystal layer is provided on a three-dimensional pattern that exposes selected areas of the first surface of the substrate.
摘要翻译：公开了一种制造发光二极管的方法。一方面，发光二极管具有载流子，III族氮化物型材料的有源层结构和III族氮化物型材料的光子晶体结构。有源层结构包括具有n型掺杂层和p型掺杂层的第一有源层，并且适当地为量子阱结构。光子晶体结构包括由一个或多个沟槽隔开的周期性分布的沟槽或周期性分布的柱。光子晶体结构包括其中沟槽直径逐渐增加的过度生长层，以及沟槽直径基本上恒定的定向光子晶体层。二极管可以以一种方法形成，其中定向光子晶体层设置在暴露基板的第一表面的选定区域的三维图案上。

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