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1. 发明申请

US20110185101A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统
公开(公告)号：US20110185101A1
公开(公告)日：2011-07-28
申请号：US13076041
申请日：2011-03-30
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

2. 发明授权

US08745306B2 Scalable distributed memory and I/O multiprocessor system 有权
标题翻译：可扩展分布式内存和I / O多处理器系统
公开(公告)号：US08745306B2
公开(公告)日：2014-06-03
申请号：US13590936
申请日：2012-08-21
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

3. 发明授权

US07058750B1 Scalable distributed memory and I/O multiprocessor system 有权
标题翻译：可扩展分布式内存和I / O多处理器系统
公开(公告)号：US07058750B1
公开(公告)日：2006-06-06
申请号：US09569100
申请日：2000-05-10
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥接器。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

4. 发明授权

US5584017A Cache control which inhibits snoop cycles if processor accessing memory is the only processor allowed to cache the memory location 失效
标题翻译：如果处理器访问存储器是允许缓存内存位置的唯一处理器，则禁止侦听周期的缓存控制
公开(公告)号：US5584017A
公开(公告)日：1996-12-10
申请号：US425351
申请日：1995-04-18
申请人： Paul R. Pierce , Anthony M. Zilka
发明人： Paul R. Pierce , Anthony M. Zilka
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0831
摘要： A multi-processor cache control system wherein cache control information is encoded into the address bits of a memory access request. The encoded cache control information is used to optimize cache control functions. Each memory access request is comprised of at least two elements. First, an address field is provided to define the location of the desired data item. Secondly, cache control information is provided in a cache control field within each memory access request. The cache control field comprises a plurality of bits that define a relationship between the address field and a plurality of local caches associated with processors in a multi-processor system. This relationship determines which of a plurality of local caches may cache the data item referenced by the address within the address field.
摘要翻译：一种多处理器高速缓存控制系统，其中高速缓存控制信息被编码到存储器访问请求的地址位中。编码高速缓存控制信息用于优化缓存控制功能。每个存储器访问请求由至少两个元素组成。首先，提供地址字段以定义所需数据项的位置。其次，在每个存储器访问请求中的高速缓存控制字段中提供高速缓存控制信息。高速缓存控制字段包括定义地址字段和与多处理器系统中的处理器相关联的多个本地高速缓存之间的关系的多个位。该关系确定多个本地高速缓存中的哪一个可以缓存由地址字段内的地址引用的数据项。

5. 发明授权

US5446915A Parallel processing system virtual connection method and apparatus with protection and flow control 失效
标题翻译：并行处理系统虚拟连接方法和装置，具有保护和流量控制
公开(公告)号：US5446915A
公开(公告)日：1995-08-29
申请号：US66579
申请日：1993-05-25
申请人： Paul R. Pierce
发明人： Paul R. Pierce
IPC分类号： G06F9/46 , G06F15/173 , H04L12/56 , G06F9/38 , G06F9/445 , G06F13/14 , G06F15/16
CPC分类号： G06F9/54 , G06F15/17337 , H04L45/00
摘要： A parallel processing system virtual connection method and apparatus with protection and flow control is described. In accordance with the present invention, virtual connections between processor nodes are maintained through the use of connection tables. Each connection table is comprised of a plurality of connection table entries with each entry defining one end of a virtual connection between two processor nodes. Each connection table entry, in turn, comprises a data structure which stores data used to define the virtual connection. The passage of messages or data is accomplished through the use of the data structures within each connection entry in conjunction with message passing hardware in the node. User processes in the processor nodes interact directly with the message passing hardware, without the need to call the operating systems.
摘要翻译：描述了具有保护和流量控制的并行处理系统虚拟连接方法和装置。根据本发明，通过使用连接表来维护处理器节点之间的虚拟连接。每个连接表由多个连接表条目组成，每个条目定义两个处理器节点之间的虚拟连接的一端。每个连接表条目又包括存储用于定义虚拟连接的数据的数据结构。消息或数据的通过是通过使用每个连接条目中的数据结构以及节点中的消息传递硬件来实现的。处理器节点中的用户进程与消息传递硬件直接交互，无需调用操作系统。

6. 发明申请

US20120317328A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统
公开(公告)号：US20120317328A1
公开(公告)日：2012-12-13
申请号：US13590936
申请日：2012-08-21
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

7. 发明授权

US07930464B2 Scalable memory and I/O multiprocessor systems 有权
标题翻译：可扩展内存和I / O多处理器系统
公开(公告)号：US07930464B2
公开(公告)日：2011-04-19
申请号：US12549491
申请日：2009-08-28
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

8. 发明授权

US08255605B2 Scalable distributed memory and I/O multiprocessor system 有权
标题翻译：可扩展分布式内存和I / O多处理器系统
公开(公告)号：US08255605B2
公开(公告)日：2012-08-28
申请号：US13076041
申请日：2011-03-30
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BICS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BICS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

9. 发明申请

US20090319717A1 SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS 有权
标题翻译：可分配的分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US20090319717A1
公开(公告)日：2009-12-24
申请号：US12549491
申请日：2009-08-28
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

10. 发明授权

US07603508B2 Scalable distributed memory and I/O multiprocessor systems and associated methods 有权
标题翻译：可扩展分布式存储器和I / O多处理器系统及相关方法
公开(公告)号：US07603508B2
公开(公告)日：2009-10-13
申请号：US12013595
申请日：2008-01-14
申请人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
发明人： Linda J. Rankin , Paul R. Pierce , Gregory E. Dermer , Wen-Hann Wang , Kai Cheng , Richard H. Hofsheier , Nitin Y. Borkar
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.
摘要翻译：多处理器系统包括至少一个处理模块，至少一个I / O模块和互连网络，以将所述至少一个处理模块与所述至少一个输入/输出模块连接。在示例实施例中，互连网络包括用于在输入/输出模块和处理模块之间发送和接收事务的至少两个桥。互连网络还包括至少两个交叉开关以通过高带宽交换机连接路由交易。使用互连网络的实施例允许处理模块和I / O模块之间的高带宽通信。标准处理模块硬件可以与互连网络一起使用，而无需修改BIOS或操作系统。此外，使用本发明的实施例的互连网络对于处理器主板是非侵入性的。处理器内存总线，时钟和复位逻辑都保持不变。

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