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    • 1. 发明授权
    • Electrical test structure and method for space and line measurement
    • 空间和线路测量的电气测试结构和方法
    • US5552718A
    • 1996-09-03
    • US368181
    • 1995-01-04
    • James A. BruceMichael S. HibbsRobert K. Leidy
    • James A. BruceMichael S. HibbsRobert K. Leidy
    • G01R31/26
    • G01R31/26
    • This describes a test pattern and method for measuring dimensional characteristics of features formed on a surface. This is realized and provided by forming a space, defined by the feature, in intersecting relationship with a pair of conductive lines of a test pattern configuration such that the lines are altered at the intersection with the space in accordance with the dimensions of that space, measuring the resistance of at least one of the lines in a region remote from the intersection with the space and the resistance of each line in the region of its intersection with the space, and comparing the resistance of the remote region with the resistances for the region of each of the lines where they intersect the space to thereby establish the position of, and at least one dimension of that space. A test structure wherein the spaced lines intersect the longitudinal ends of the space is utilized for determining the length and the longitudinal position of the space, and a test structure where lines intersect the lateral edges of the space is utilized for determining the width of and the lateral position of the space. For measuring the dimensional characteristics of a line feature, the above noted patterns are utilized, after first replicating the line as a space.
    • 这描述了用于测量在表面上形成的特征的尺寸特性的测试图案和方法。 这通过以与测试图案配置的一对导线相交的方式形成由特征限定的空间来实现并提供,使得根据该空间的尺寸在与空间的交叉处改变线, 测量远离与该空间相交的区域的空间和电阻的区域中的至少一条线路的电阻,并将该偏移区域的电阻与该区域的电阻进行比较 其中它们与空间相交的每条线,从而建立该空间的位置和至少一个维度。 用于确定空间的长度和纵向位置的测量结构,其中与空间的纵向端部相交的间隔线用于确定空间的横向边缘的线和与该空间的横向边缘相交的测试结构, 横向位置的空间。 为了测量线特征的尺寸特征,在首先将线复制为空间之后,利用上述图案。
    • 2. 发明授权
    • Method of photolithographically defining three regions with one mask
step and self aligned isolation structure formed thereby
    • 用一个掩模步骤和由此形成的自对准隔离结构光刻地限定三个区域的方法
    • US6147394A
    • 2000-11-14
    • US172366
    • 1998-10-14
    • James A. BruceSteven J. HolmesRobert K. LeidyWalter E. MlynkoEdward W. Sengle
    • James A. BruceSteven J. HolmesRobert K. LeidyWalter E. MlynkoEdward W. Sengle
    • G03F7/004G03F1/00G03F7/095G03F7/20H01L21/027H01L21/302H01L21/3065H01L21/76H01L21/762H01L29/00
    • G03F7/70633G03F7/095G03F7/2022G03F7/2024H01L21/0274H01L21/762
    • The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.
    • 本发明的优选实施例提供了一种使用单个掩蔽步骤在半导体衬底上限定三个区域的方法。 优选实施例使用光刻胶材料,同时具有曝光的正色调和负色调响应。 这种材料的组合可以提供一种新型的抗蚀剂,我们称之为混合抗蚀剂。 混合抗蚀剂包含作用于第一光化能级的正色调成分和以第二光化能级起作用的负色调成分,其中第一和第二光化能级被光化能的中间范围分隔。 当混合抗蚀剂暴露于光化能时,受到完全曝光的抗蚀剂的区域交联以形成负色调线图案,未曝光形式的区域保持光活性并形成正色调图案,并且暴露于 中间量的辐射在开发过程中变得可溶并被冲走。 这暴露了掩码上的第一个区域。 然后毯子暴露混合抗蚀剂,正色调图案变得可溶,并且在显影过程中将被洗掉。 这掩盖了掩模上的第二区域,第三区域仍被混合抗蚀剂覆盖。 因此,优选实施例能够使用单个掩蔽步骤来定义三个区域,而不会叠加错误。
    • 4. 发明授权
    • Method for improving visibility of alignment target in semiconductor
processing
    • 用于提高半导体处理中的对准目标的可见性的方法
    • US06015750A
    • 2000-01-18
    • US7694
    • 1998-01-15
    • James A. BruceSteven John HolmesRobert K. Leidy
    • James A. BruceSteven John HolmesRobert K. Leidy
    • H01L23/544G01B11/27
    • H01L23/544H01L2223/54453H01L2924/0002
    • Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets. All of these embodiments result in a contrast between the alignment target and the adjacent material that is more consistent over variations in oxide thickness. The more uniform contrast makes it easier for the stepper system to identify the edges of the alignment targets, resulting in a more exact placement of the mask.
    • 公开了增强半导体晶片上的对准目标和相邻材料之间的对比度的方法。 根据第一实施例,在较早处理步骤期间沉积的TiN层被剥离以增强金属层的反射率。 根据第二实施例,在金属层上添加反射涂层以增强金属层的反射率。 根据第三实施例,在整个晶片上添加反射涂层以增强金属层的反射率。 根据第四实施例,添加夹层结构中的抗反射涂层以降低邻近对准靶的材料的反射率。 根据第五实施例,添加有机抗反射涂层以降低邻近对准靶的材料的反射率。 所有这些实施例导致对准目标和相邻材料之间的对比度,其与氧化物厚度的变化更一致。 更均匀的对比度使得步进系统更容易识别对准目标的边缘,导致掩模更准确的放置。
    • 6. 发明授权
    • Method for improving visibility of alignment targets in semiconductor
processing
    • 用于提高半导体处理中的对准目标的可见性的方法
    • US5760483A
    • 1998-06-02
    • US772709
    • 1996-12-23
    • James A. BruceSteven John HolmesRobert K. Leidy
    • James A. BruceSteven John HolmesRobert K. Leidy
    • H01L23/544
    • H01L23/544H01L2223/54453H01L2924/0002
    • Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets. All of these embodiments result in a contrast between the alignment target and the adjacent material that is more consistent over variations in oxide thickness. The more uniform contrast makes it easier for the stepper system to identify the edges of the alignment targets, resulting in a more exact placement of the mask.
    • 公开了增强半导体晶片上的对准目标和相邻材料之间的对比度的方法。 根据第一实施例,在较早处理步骤期间沉积的TiN层被剥离以增强金属层的反射率。 根据第二实施例,在金属层上添加反射涂层以增强金属层的反射率。 根据第三实施例,在整个晶片上添加反射涂层以增强金属层的反射率。 根据第四实施例,添加夹层结构中的抗反射涂层以降低邻近对准靶的材料的反射率。 根据第五实施例,添加有机抗反射涂层以降低邻近对准靶的材料的反射率。 所有这些实施例导致对准目标和相邻材料之间的对比度,其与氧化物厚度的变化更一致。 更均匀的对比度使得步进系统更容易识别对准目标的边缘,导致掩模更准确的放置。
    • 7. 发明授权
    • Mask defect analysis system
    • 面膜缺陷分析系统
    • US07492940B2
    • 2009-02-17
    • US11761856
    • 2007-06-12
    • James A. BruceOrest BulaEdward W. ConradWilliam C. LeipoldMichael S. HibbsJoshua J. Krueger
    • James A. BruceOrest BulaEdward W. ConradWilliam C. LeipoldMichael S. HibbsJoshua J. Krueger
    • G06K9/00
    • G03F1/84
    • An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
    • 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合,以确定何时发生了给定掩模层上的缺陷。 掩模检查结果包括缺陷的存在,位置和类型(透明或不透明)。 最终,根据缺陷是否可能导致产品故障,确定是否废除,修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
    • 8. 发明授权
    • Mask defect analysis system
    • 面膜缺陷分析系统
    • US07257247B2
    • 2007-08-14
    • US09683836
    • 2002-02-21
    • James A. BruceOrest BulaEdward W. ConradWilliam C. LeipoldMichael S. HibbsJoshua J. Krueger
    • James A. BruceOrest BulaEdward W. ConradWilliam C. LeipoldMichael S. HibbsJoshua J. Krueger
    • G06K9/00
    • G03F1/84
    • An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
    • 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合,以确定给定掩模层上的缺陷何时发生。 掩模检查结果包括缺陷的存在,位置和类型(透明或不透明)。 最终,根据缺陷是否可能导致产品故障,确定是否废除,修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
    • 10. 发明授权
    • Mask with linewidth compensation and method of making same
    • 具有线宽补偿的掩模及其制作方法
    • US06338921B1
    • 2002-01-15
    • US09479150
    • 2000-01-07
    • James A. BruceDavid V. HorakRandy W. MannJed H. RankinAndrew J. Watts
    • James A. BruceDavid V. HorakRandy W. MannJed H. RankinAndrew J. Watts
    • G03F102
    • G03F7/0035G03F1/36
    • A mask (50′) with linewidth compensation and a method of making same. The mask provides for optimized imaging of isolated patterns (64) and nested patterns (70) present on the same mask. The compensated mask is formed from an uncompensated mask (50) and comprises an upper surface (56) upon which the isolated and nested patterns are formed. The isolated pattern comprises a first segment (76) having first sidewalls (76S). The nested pattern comprises second segments (72) proximate each other and having second sidewalls (72S). A partial conformal layer (86) covers the first segment and has feet (90) outwardly extending a distance d from the first sidewalls along the upper surface. The feet are preferably of a thickness that partially transmits exposure light.
    • 具有线宽补偿的掩模(50')及其制造方法。 掩模提供对同一掩模上存在的孤立图案(64)和嵌套图案(70)的优化成像。 补偿掩模由未补偿的掩模(50)形成,并且包括形成隔离和嵌套图案的上表面(56)。 隔离图案包括具有第一侧壁(76S)的第一段(76)。 嵌套图案包括彼此靠近并具有第二侧壁(72S)的第二段(72)。 部分保形层(86)覆盖第一段并且具有沿着上表面向外延伸距离第一侧壁的距离d的脚(90)。 脚部优选地具有部分地透射曝光光的厚度。