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1. 发明授权

US08619236B2 Determining lithographic set point using optical proximity correction verification simulation 失效
标题翻译：使用光学邻近校正验证模拟确定光刻设定点
公开(公告)号：US08619236B2
公开(公告)日：2013-12-31
申请号：US12953511
申请日：2010-11-24
申请人： James A. Bruce , Edward W. Conrad , Jacek G. Smolinski
发明人： James A. Bruce , Edward W. Conrad , Jacek G. Smolinski
IPC分类号： G03B27/32 , G03B27/68 , G03B27/52 , G03B27/42
CPC分类号： G03F1/36 , G03F7/705
摘要： The subject matter disclosed herein relates to determining a lithographic set point using simulations of optical proximity correction verification. In one embodiment, a computer-implemented method of determining a lithographic tool set point for a lithographic process is disclosed. The method may include: providing a model of a production lithographic process including simulations of printed shapes; analyzing the model of the production lithographic process to determine whether a set of structures on a production mask used in the production lithographic process to create the printed shapes will fail under a plurality of set points; determining an operating region of set points where the set of structures on the production mask does not fail; and establishing a set point location within the operating region based upon a set point selection function.
摘要翻译：本文公开的主题涉及使用光学邻近校正验证的模拟来确定光刻设置点。在一个实施例中，公开了一种用于确定光刻工艺的光刻工具设定点的计算机实现的方法。该方法可以包括：提供生产平版印刷工艺的模型，包括印刷形状的模拟; 分析生产光刻工艺的模型，以确定在生产光刻工艺中用于产生印刷形状的生产掩模上的一组结构是否将在多个设定点下失效; 确定生产掩模上的一组结构不失败的设定点的操作区域; 以及基于设定点选择功能在操作区域内建立设定点位置。

2. 发明授权

US08577489B2 Diagnosing in-line critical dimension control adjustments using optical proximity correction verification 失效
标题翻译：使用光学邻近校正验证诊断在线临界尺寸控制调整
公开(公告)号：US08577489B2
公开(公告)日：2013-11-05
申请号：US13014152
申请日：2011-01-26
申请人： James A. Bruce , Kenneth T. Settlemyer, Jr.
发明人： James A. Bruce , Kenneth T. Settlemyer, Jr.
IPC分类号： G06F19/00
CPC分类号： G03F1/36 , G03F1/70 , G03F7/705
摘要： Solutions for diagnosing in-line critical dimension control adjustments in a lithographic process are disclosed. In one embodiment, a method includes: locating a control structure in a data set representing one of a chip or a kerf; simulating component dimensions within a region proximate to the control structure; determining a difference between the simulated component dimensions within the region and target component dimensions within the region; determining whether the difference exceeds a predetermined tolerance threshold; adjusting a simulation condition in response to determining the difference exceeds the predetermined tolerance threshold; and repeating the simulating of the component dimensions within the region, the determining of the difference, and the determining of whether the difference exceeds the predetermined tolerance threshold in response to the adjusting of the simulation condition.
摘要翻译：公开了用于诊断光刻工艺中的在线临界尺寸控制调整的解决方案。在一个实施例中，一种方法包括：将控制结构定位在表示芯片或切口之一的数据集中; 在靠近控制结构的区域内模拟部件尺寸; 确定区域内的模拟部件尺寸与该区域内的目标部件尺寸之间的差异; 确定所述差异是否超过预定的容差阈值; 响应于确定所述差异来调整模拟条件超过所述预定公差阈值; 并且响应于所述模拟条件的调整，重复所述区域内的所述分量尺寸的模拟，所述差的确定以及所述差是否超过所述预定公差阈值。

3. 发明申请

US20110173586A1 METHOD FOR CREATING ELECTRICALLY TESTABLE PATTERNS 有权
标题翻译：创建电气可测图案的方法
公开(公告)号：US20110173586A1
公开(公告)日：2011-07-14
申请号：US12687147
申请日：2010-01-14
申请人： James A. Bruce , Edward W. Conrad , Jacek G. Smolinski
发明人： James A. Bruce , Edward W. Conrad , Jacek G. Smolinski
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36 , G03F1/84 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method and computer program product for designing an electrically testable pattern that is based on patterns derived from the desired chip layout to be printed. Such electrical test patterns are based on the features within a region of influence around critical sites. The critical sites may be identified, for example, by processing the chip layout through an OPC verification tool that flags potential failure sites. The electrical test pattern is formed from features within an region of influence (ROI) around the critical site, and also include electrical feed lines at terminal ends of one or more features having an electrical characteristic that is sensitive to changes in the printed environment of the critical site. The feed lines may be locate on the same or a different layer than the critical site, depending on the chip design. The electrical pattern is further defined by retaining features within a second trim region such that the printed features within the ROI are not substantially modified by the absence of features outside the second trim region.
摘要翻译：本发明提供一种用于设计基于从要打印的所需芯片布局导出的图案的电可测图案的方法和计算机程序产品。这种电气测试模式基于围绕关键场所的影响区域内的特征。可以通过例如标记潜在故障位置的OPC验证工具来处理芯片布局来识别关键位置。电测试图案由围绕关键位置的影响区域（ROI）内的特征形成，并且还包括在一个或多个特征的终端处的电馈线，其具有对于印刷环境的变化敏感的电特性关键站点。取决于芯片设计，馈线可以位于与关键位置相同或不同的层上。通过在第二修剪区域内保持特征来进一步限定电气图案，使得ROI内的印刷特征基本上不被第二修剪区域外的特征缺失地修改。

4. 发明申请

US20080141211A1 OPC VERIFICATION USING AUTO-WINDOWED REGIONS 失效
标题翻译：使用自动窗口区域进行OPC验证
公开(公告)号：US20080141211A1
公开(公告)日：2008-06-12
申请号：US11609033
申请日：2006-12-11
申请人： James A. Bruce , Gregory J. Dick , Donald P. Perley , Jacek G. Smolinski
发明人： James A. Bruce , Gregory J. Dick , Donald P. Perley , Jacek G. Smolinski
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method is provided for performing optical proximity correction (“OPC”) verification in which features of concern of a photomask are identified using data relating to shapes of the photomask, an aerial image to be obtained using the photomask, or a photoresist image to be obtained in a photoimageable layer using the photomask. A plurality of areas of the photomask, aerial image or photoresist image are identified which incorporate the identified features of concern, where the plurality of identified areas occupy substantially less area than the total area of the photomask that is occupied by features. Enhanced OPC verification limited to the plurality of identified areas is then performed to identify problems of at least one of the photomask, aerial image or photoresist image.
摘要翻译：提供了一种用于执行光学邻近校正（“OPC”）验证的方法，其中使用与光掩模的形状，使用光掩模获得的空间图像或光致抗蚀剂图像相关联的数据来识别光掩模的特征使用光掩模在可光成像层中获得。识别光掩模，空中图像或光致抗蚀剂图像的多个区域，其包含所识别的关注特征，其中多个识别区域占据占据特征的光掩模的总面积的面积实质上更小的面积。然后执行限于多个所识别的区域的增强的OPC验证，以识别光掩模，空中图像或光致抗蚀剂图像中的至少一个的问题。

5. 发明授权

US06766507B2 Mask/wafer control structure and algorithm for placement 失效
标题翻译：掩模/晶片控制结构和放置算法
公开(公告)号：US06766507B2
公开(公告)日：2004-07-20
申请号：US10121811
申请日：2002-04-12
申请人： James A. Bruce , Stephen E. Knight , Joshua J. Krueger , Matthew C. Nicholls , Jed H. Rankin
发明人： James A. Bruce , Stephen E. Knight , Joshua J. Krueger , Matthew C. Nicholls , Jed H. Rankin
IPC分类号： G06F1750
CPC分类号： G03F7/70625 , G03F7/70433 , G03F7/70683
摘要： A mask/wafer control structure and an algorithm for placement thereof provide for data placement of measurement control structures, called a PLS, Process limiting Structure, on a mask and a plurality of chips on the wafer which provide for tighter control of both mask manufacture and wafer production by providing the most critical design structures for measurement during creation of the mask, and in the photolithography and etch processes. The PLS structures are located at multiple locations throughout the chip, and so they receive the same data preparation as the chip, and measurement tools are able to measure the same features at each fabrication step from fabrication of the mask to final formation of the etched features. Manufacturing control and the interlock between the wafer fabrication and the mask fabrication are enhanced, allowing for improved quality of the final product.
摘要翻译：掩模/晶片控制结构及其放置算法提供在晶片上的掩模和多个芯片上的称为PLS，过程限制结构的测量控制结构的数据放置，其提供对掩模制造和在制作掩模期间以及在光刻和蚀刻工艺中提供用于测量的最关键的设计结构的晶片生产。 PLS结构位于整个芯片的多个位置，因此它们接收与芯片相同的数据准备，并且测量工具能够在从制造掩模到最终形成蚀刻特征的每个制造步骤处测量相同的特征。增强制造控制和晶片制造与掩模制造之间的互锁，从而允许最终产品的质量提高。

6. 发明授权

US06395438B1 Method of etch bias proximity correction 失效
标题翻译：蚀刻偏置接近校正方法
公开(公告)号：US06395438B1
公开(公告)日：2002-05-28
申请号：US09756540
申请日：2001-01-08
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F1/80 , G03F7/70433
摘要： A method for including etch bias corrections in pre-processing of integrated circuit design data to compensate for deviations introduced during lithographic printing and etching. The design data is segmented, and etch bias corrections are applied to the segments based on their proximity to adjacent design features. Adjusted or corrected design data is produced which may be used to create a mask which includes etch bias corrections for better fidelity and reproduction of the original design in the etching step. Etch bias corrections may also be applied based upon characteristics of regions defined in the design, or on a pattern density of the design.
摘要翻译：一种在集成电路设计数据的预处理中包括蚀刻偏差校正以补偿在平版印刷和蚀刻期间引入的偏差的方法。设计数据被分段，并且基于它们与相邻设计特征的接近度，将蚀刻偏差校正应用于段。产生调整或校正的设计数据，其可用于创建掩模，该掩模包括用于在蚀刻步骤中更好保真度和再现原始设计的蚀刻偏差校正。也可以基于设计中定义的区域的特征或设计的图案密度来应用蚀刻偏差校正。

7. 发明授权

US4978594A Fluorine-containing base layer for multi-layer resist processes 失效
标题翻译：含氟基底层用于多层抗蚀剂工艺
公开(公告)号：US4978594A
公开(公告)日：1990-12-18
申请号：US258530
申请日：1988-10-17
申请人： James A. Bruce , Michael L. Kerbaugh , Ranee W. Kwong , Tanya N. Lee , Harold G. Linde , Harbans S. Sachdev
发明人： James A. Bruce , Michael L. Kerbaugh , Ranee W. Kwong , Tanya N. Lee , Harold G. Linde , Harbans S. Sachdev
IPC分类号： H01L21/302 , G03F7/09 , G03F7/40 , H01L21/027 , H01L21/3065
CPC分类号： G03F7/094 , G03F7/405
摘要： A process for forming a pattern on a substrate utilizing photolithographic techniques. In this process a layer of polymeric material containing a fluorine-containing compound is applied over the substrate and cured. A layer of photoresist material is applied over the polymeric material imagewise exposed and developed to reveal the image on the underlying polymeric material. Thereafter, the photoresist is silylated, and the structure is reactive ion etched to transfer the pattern to the underlying substrate. The fluorine component provides an underlying structure free of residue and cracking.

8. 发明授权

US07492940B2 Mask defect analysis system 失效
标题翻译：面膜缺陷分析系统
公开(公告)号：US07492940B2
公开(公告)日：2009-02-17
申请号：US11761856
申请日：2007-06-12
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
摘要翻译：提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定何时发生了给定掩模层上的缺陷。掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。

9. 发明授权

US07269808B2 Design verification 失效
标题翻译：设计验证
公开(公告)号：US07269808B2
公开(公告)日：2007-09-11
申请号：US10908786
申请日：2005-05-26
申请人： James A. Bruce , James A. Culp , John D. Nickel , Jacek G. Smolinski
发明人： James A. Bruce , James A. Culp , John D. Nickel , Jacek G. Smolinski
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.
摘要翻译：一种设计验证方法，包括（a）在设计中提供与设计导电线直接物理接触的设计导电线和设计接触区; （b）对设计导电线的模拟导电线进行建模; （c）模拟设计接触区域的可能的接触区域，其中设计接触区域和可能的接触区域不相同; 以及（d）如果所述模拟导电线路和所述可能接触区域的接口表面积小于预定值，则确定所述设计导电线路和所述设计接触区域具有潜在的缺陷。

10. 发明授权

US06395624B1 Method for forming implants in semiconductor fabrication 失效
标题翻译：在半导体制造中形成植入物的方法
公开(公告)号：US06395624B1
公开(公告)日：2002-05-28
申请号：US09253952
申请日：1999-02-22
申请人： James A. Bruce , Randy W. Mann
发明人： James A. Bruce , Randy W. Mann
IPC分类号： H01L21336
CPC分类号： H01L21/223 , H01L21/268 , Y10S438/952
摘要： The present invention provides a novel method of forming implants with Projection Gas-Immersion Laser Doping (PGILD) process that overcomes the disadvantages of the prior art methods. In particular, the preferred method applies a reflective coating over features before the application of the PGILD laser. The reflective coating lowers the amount of heat absorbed by the features, improving the reliability of the fabrication process. The preferred method is particularly applicable to the fabrication of field effect transistors (FETs). In this application, a gate stack is formed, and a reflective coating is over the gate stack. An anti-reflective coating (ARC) is then applied over the reflective coating. The anti-reflective coating reduces variability of the photolithographic process used to pattern the gate stack. After the gate stack is patterned, the anti-reflective coating is removed, leaving the reflective coating on the gate stack. The PGILD process can then be used to form source/drain doped regions on the transistors. The reflective coating reduces the amount of heat absorbed by the gate stack, and thus provides an improved method for fabricating transistors.
摘要翻译：本发明提供了一种克服现有技术方法的缺点的用投影气体浸渍激光掺杂（PGILD）工艺形成植入物的新方法。特别地，优选的方法在施加PGILD激光器之前对反射涂层施加特征。反射涂层降低了由特征吸收的热量，提高了制造工艺的可靠性。优选的方法特别适用于场效应晶体管（FET）的制造。在这种应用中，形成栅极叠层，并且反射涂层在栅极叠层上方。然后将抗反射涂层（ARC）涂覆在反射涂层上。抗反射涂层降低了用于对栅极堆叠进行图案化的光刻工艺的变化。在栅极堆叠被图案化之后，去除抗反射涂层，使反射涂层留在栅极叠层上。然后可以使用PGILD工艺在晶体管上形成源极/漏极掺杂区域。反射涂层减少了栅叠层吸收的热量，因此提供了一种制造晶体管的改进方法。

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