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1. 发明授权

US07060583B2 Method for manufacturing a bipolar transistor having a polysilicon emitter 有权
标题翻译：一种制造具有多晶硅发射极的双极晶体管的方法
公开(公告)号：US07060583B2
公开(公告)日：2006-06-13
申请号：US10757360
申请日：2004-01-13
申请人： Jakob Kriz , Martin Seck , Armin Tilke
发明人： Jakob Kriz , Martin Seck , Armin Tilke
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/66272 , H01L21/2257
摘要： In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an insulating material will now be applied, wherein the at least one layer is patterned such that at least one section of the basis region is exposed. Next, a layer of a polycrystalline semiconductor material of the first conductivity type, which is heavily doped with doping atoms, will be generated such that the exposed section is essentially covered. Now, a second layer of a highly conductive material on the layer of the polycrystalline semiconductor material will be generated in order to form an emitter double layer with the same. Thereupon, at least part of the doping atoms of the first conductivity type of the heavily doped polycrystalline semiconductor layer is caused to get into the basis region to generate an emitter region of the first conductivity type.
摘要翻译：在本发明的制造具有多晶硅发射极的双极晶体管的方法中，首先将产生第一导电类型的集电极区域，并与其邻接的第二导电类型的基极区域。现在将施加至少一层绝缘材料，其中图案化至少一个层使得基础区域的至少一个部分被暴露。接下来，将产生重掺杂掺杂原子的第一导电类型的多晶半导体材料层，使得暴露部分基本上被覆盖。现在，将产生多晶半导体材料层上的高导电材料的第二层，以便形成具有该多层半导体材料的发射极双层。因此，引起重掺杂多晶半导体层的第一导电类型的掺杂原子的至少一部分进入基区以产生第一导电类型的发射极区。

2. 发明授权

US07091100B2 Polysilicon bipolar transistor and method of manufacturing it 有权
标题翻译：多晶硅双极晶体管及其制造方法
公开(公告)号：US07091100B2
公开(公告)日：2006-08-15
申请号：US10916774
申请日：2004-08-12
申请人： Uwe Rudolph , Martin Seck , Armin Tilke
发明人： Uwe Rudolph , Martin Seck , Armin Tilke
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/42304
摘要： In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched in the base terminal layer using the etch stop layer as an etch stop.
摘要翻译：在制造用于双极晶体管的基极端子结构的本发明方法中，将蚀刻停止层施加在单晶半导体衬底上，在蚀刻停止层上产生多晶硅基极端子层，并且在其中蚀刻发射极窗口基底端层使用蚀刻停止层作为蚀刻停止层。

3. 发明申请

US20050106829A1 Polysilicon bipolar transistor and method of manufacturing it 有权
标题翻译：多晶硅双极晶体管及其制造方法
公开(公告)号：US20050106829A1
公开(公告)日：2005-05-19
申请号：US10916774
申请日：2004-08-12
申请人： Uwe Rudolph , Martin Seck , Armin Tilke
发明人： Uwe Rudolph , Martin Seck , Armin Tilke
IPC分类号： H01L21/331 , H01L29/10 , H01L29/423 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/42304
摘要： In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched in the base terminal layer using the etch stop layer as an etch stop.
摘要翻译：在制造用于双极晶体管的基极端子结构的本发明方法中，将蚀刻停止层施加在单晶半导体衬底上，在蚀刻停止层上产生多晶硅基极端子层，并且在其中蚀刻发射极窗口基底端层使用蚀刻停止层作为蚀刻停止层。

4. 发明授权

US07964494B2 Integrated connection arrangements 有权
标题翻译：集成连接布置
公开(公告)号：US07964494B2
公开(公告)日：2011-06-21
申请号：US12562475
申请日：2009-09-18
申请人： Stefan Drexl , Thomas Goebel , Johann Helneder , Martina Hommel , Wolfgang Klein , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck
发明人： Stefan Drexl , Thomas Goebel , Johann Helneder , Martina Hommel , Wolfgang Klein , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck
IPC分类号： H01L21/4763
CPC分类号： H01L24/05 , H01L23/53228 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01061 , H01L2924/01068 , H01L2924/01073 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2224/45099
摘要： A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
摘要翻译：提供一种具有至少部分或全部布置在电绝缘层的切口中的外部导电结构的连接装置。内导电结构设置在绝缘层一侧的切口的底部。内部导电结构在接触区域中邻接外部导电结构。接触区域设置在切口的另一侧的外部导电结构。接触区域和接触区域不重叠。切口的底部布置成与接触区域的至少一半重叠，以在接触区域和内部导电结构之间的主电流路径外侧的切口的边缘处的绝缘层中提供台阶。

5. 发明授权

US07656037B2 Integrated circuit with improved component interconnections 有权
标题翻译：具有改进的组件互连的集成电路
公开(公告)号：US07656037B2
公开(公告)日：2010-02-02
申请号：US11525113
申请日：2006-09-21
申请人： Martina Hommel , Heinrich Koerner , Markus Schwerd , Martin Seck
发明人： Martina Hommel , Heinrich Koerner , Markus Schwerd , Martin Seck
IPC分类号： H01S5/00 , H01S3/13 , H01L23/52 , H01L23/522 , H01L27/08 , H01L23/64
CPC分类号： H01L23/5227 , H01L23/5225 , H01L23/60 , H01L2223/6622 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.
摘要翻译：公开了一种集成电路装置。在一个实施例中，集成电路装置包括至少三个导电结构层和细长互连。

6. 发明申请

US20080227261A1 METHOD FOR FABRICATING A TRANSISTOR STRUCTURE 有权
标题翻译：制造晶体管结构的方法
公开(公告)号：US20080227261A1
公开(公告)日：2008-09-18
申请号：US12051928
申请日：2008-03-20
申请人： Josef Bock , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schafer , Martin Seck
发明人： Josef Bock , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schafer , Martin Seck
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L21/8222 , H01L27/0825 , H01L29/0821
摘要： The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths.The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high-frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for a high-voltage transistor with increased breakdown voltages.
摘要翻译：本发明涉及一种用于制造晶体管结构的方法，该方法至少包括具有不同集电极宽度的第一和第二双极晶体管。本发明的区别在于，不同掺杂区域之间的所有结点都具有尖锐的界面。在这种情况下，作为示例，第一集电极区域2.1适用于具有高限制频率f T T的高频晶体管，并且第二集电极区域2.2适用于具有增加击穿电压。

7. 发明申请

US20060192289A1 Integrated connection arrangements 有权
公开(公告)号：US20060192289A1
公开(公告)日：2006-08-31
申请号：US11350518
申请日：2006-02-09
申请人： Stefan Drexl , Thomas Goebel , Johann Helneder , Martina Hommel , Wolfgang Klein , Heinrich Korner , Andrea Mitchell , Markus Schwerd , Martin Seck
发明人： Stefan Drexl , Thomas Goebel , Johann Helneder , Martina Hommel , Wolfgang Klein , Heinrich Korner , Andrea Mitchell , Markus Schwerd , Martin Seck
IPC分类号： H01L23/52
CPC分类号： H01L24/05 , H01L23/53228 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01061 , H01L2924/01068 , H01L2924/01073 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2224/45099
摘要： A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

8. 发明授权

US07667256B2 Integrated circuit arrangement having a plurality of conductive structure levels and capacitor, and a method for producing the integrated circuit arrangement 有权
标题翻译：具有多个导电结构等级和电容器的集成电路装置，以及用于制造集成电路装置的方法
公开(公告)号：US07667256B2
公开(公告)日：2010-02-23
申请号：US11525111
申请日：2006-09-21
申请人： Martina Hommel , Heinrich Koerner , Markus Schwerd , Martin Seck
发明人： Martina Hommel , Heinrich Koerner , Markus Schwerd , Martin Seck
IPC分类号： H01L43/00
CPC分类号： H01L23/5227 , H01L21/76838 , H01L23/5225 , H01L23/60 , H01L2223/6622 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.
摘要翻译：公开了一种集成电路装置。在一个实施例中，集成电路装置包括至少三个导电结构层，其中在每种情况下布置细长互连。

9. 发明授权

US07371650B2 Method for producing a transistor structure 有权
标题翻译：晶体管结构的制造方法
公开(公告)号：US07371650B2
公开(公告)日：2008-05-13
申请号：US10532894
申请日：2003-10-24
申请人： Josef Böck , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schäfer , Martin Seck
发明人： Josef Böck , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schäfer , Martin Seck
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L21/8222 , H01L27/0825 , H01L29/0821
摘要： A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.
摘要翻译：提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域层和在第二掩埋层上具有第二集电极宽度的第二集电极区。在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。在第一收集器区域上产生具有第二厚度的第二收集器区域。产生至少一个绝缘区域，其至少隔离收集器区域彼此。

10. 发明申请

US20060009002A1 Method for producing a transistor structure 有权
标题翻译：晶体管结构的制造方法
公开(公告)号：US20060009002A1
公开(公告)日：2006-01-12
申请号：US10532894
申请日：2003-10-24
申请人： Josef Bock , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schafer , Martin Seck
发明人： Josef Bock , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schafer , Martin Seck
IPC分类号： H01L21/331 , H01L21/8228
CPC分类号： H01L29/66272 , H01L21/8222 , H01L27/0825 , H01L29/0821
摘要： A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.
摘要翻译：提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域层和在第二掩埋层上具有第二集电极宽度的第二集电极区。在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。在第一收集器区域上产生具有第二厚度的第二收集器区域。产生至少一个绝缘区域，其至少隔离收集器区域彼此。

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