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1. 发明授权

US07964494B2 Integrated connection arrangements 有权
标题翻译：集成连接布置
公开(公告)号：US07964494B2
公开(公告)日：2011-06-21
申请号：US12562475
申请日：2009-09-18
申请人： Stefan Drexl , Thomas Goebel , Johann Helneder , Martina Hommel , Wolfgang Klein , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck
发明人： Stefan Drexl , Thomas Goebel , Johann Helneder , Martina Hommel , Wolfgang Klein , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck
IPC分类号： H01L21/4763
CPC分类号： H01L24/05 , H01L23/53228 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01061 , H01L2924/01068 , H01L2924/01073 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2224/45099
摘要： A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
摘要翻译：提供一种具有至少部分或全部布置在电绝缘层的切口中的外部导电结构的连接装置。内导电结构设置在绝缘层一侧的切口的底部。内部导电结构在接触区域中邻接外部导电结构。接触区域设置在切口的另一侧的外部导电结构。接触区域和接触区域不重叠。切口的底部布置成与接触区域的至少一半重叠，以在接触区域和内部导电结构之间的主电流路径外侧的切口的边缘处的绝缘层中提供台阶。

2. 发明授权

US07233053B2 Integrated semiconductor product with metal-insulator-metal capacitor 有权
标题翻译：集成半导体产品与金属 - 绝缘体 - 金属电容器
公开(公告)号：US07233053B2
公开(公告)日：2007-06-19
申请号：US10865463
申请日：2004-06-10
申请人： Klaus Koller , Heinrich Körner , Michael Schrenk
发明人： Klaus Koller , Heinrich Körner , Michael Schrenk
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L28/75 , H01L21/76838 , H01L28/55
摘要： To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a first electrode (2, 3, 5). This auxiliary layer (6) is then opened up (15) via the first electrode. Then, a dielectric layer (7) is produced, and the metal track stack (8, 9, 10) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.
摘要翻译：为了制造具有集成金属 - 绝缘体 - 金属电容器的集成半导体产品，首先将介电辅助层（6）沉积在第一电极（2,3,5）上。然后，该辅助层（6）经由第一电极打开（15）。然后，制造电介质层（7），然后将用于第二电极的金属轨道堆叠（8,9,10）施加到电介质层（6）。然后使用已知的蚀刻工艺对金属 - 绝缘体 - 金属电容器进行图案化。这使得可以使用可以根据需要选择的材料来制造任何所需厚度的介电电容器层。特别地，这具有以下优点：通过蚀刻可以比现有技术更容易地进行蚀刻，因为不需要通过金属轨道上方的残余介电电容器层进行蚀刻。

3. 发明申请

US20100007027A1 INTEGRATED CONNECTION ARRANGEMENTS 有权
标题翻译：集成连接安排
公开(公告)号：US20100007027A1
公开(公告)日：2010-01-14
申请号：US12562475
申请日：2009-09-18
申请人： Stephen Drexl , Thomas Goebel , Johann Helneder , Martina Hommel , Wolfgang Klein , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck
发明人： Stephen Drexl , Thomas Goebel , Johann Helneder , Martina Hommel , Wolfgang Klein , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck
IPC分类号： H01L23/528
CPC分类号： H01L24/05 , H01L23/53228 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01061 , H01L2924/01068 , H01L2924/01073 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2224/45099
摘要： A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
摘要翻译：提供一种具有至少部分或全部布置在电绝缘层的切口中的外部导电结构的连接装置。内导电结构设置在绝缘层一侧的切口的底部。内部导电结构在接触区域中邻接外部导电结构。接触区域设置在切口的另一侧的外部导电结构。接触区域和接触区域不重叠。切口的底部布置成与接触区域的至少一半重叠，以在接触区域和内部导电结构之间的主电流路径外侧的切口的边缘处的绝缘层中提供台阶。

4. 发明申请

US20100129977A1 INTEGRATED CIRCUIT WITH CAPACITOR AND METHOD FOR THE PRODUCTION THEREOF 有权
标题翻译：具有电容器的集成电路及其生产方法
公开(公告)号：US20100129977A1
公开(公告)日：2010-05-27
申请号：US12696811
申请日：2010-01-29
申请人： Thomas Goebel , Johann Helneder , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck , Holger Torwesten
发明人： Thomas Goebel , Johann Helneder , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck , Holger Torwesten
IPC分类号： H01L21/77 , H01L21/02
CPC分类号： H01L28/40 , H01L21/31687 , H01L23/5223 , H01L23/5228 , H01L27/016 , H01L27/0802 , H01L27/0805 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.
摘要翻译：提出了一种集成电路和制造方法。集成电路包括在基极和覆盖电极之间包含基极，覆盖电极和电介质的电容器。电介质包含可以通过阳极氧化产生的基极中包含的材料的氧化物。电介质的外围边缘被覆盖电极覆盖。电容器上的基极层包括与电介质相邻的切口。在制造过程中，基层保护待化学物质被阳极氧化的基底材料，并且保护周围区域免受阳极氧化。可以与电容器同时制造精密电阻器。

5. 发明授权

US06958509B2 Integrated semiconductor product comprising a metal-insulator-metal capacitor 有权
标题翻译：包括金属 - 绝缘体 - 金属电容器的集成半导体产品
公开(公告)号：US06958509B2
公开(公告)日：2005-10-25
申请号：US10865000
申请日：2004-06-10
申请人： Heinrich Körner , Michael Schrenk , Markus Schwerd
发明人： Heinrich Körner , Michael Schrenk , Markus Schwerd
IPC分类号： H01L21/02 , H01L21/768 , H01L27/108
CPC分类号： H01L28/55 , H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer (5) and a dielectric auxiliary layer (16) are deposited on a first electrode (2). The protective layer and the auxiliary layer (16) are then opened up (17) via the first electrode. Then, a dielectric layer (6) is produced, and the metal track stack (7, 8, 9) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.
摘要翻译：为了制造具有集成金属 - 绝缘体 - 金属电容器的集成半导体产品，首先在第一电极（2）上沉积介电保护层（5）和介电辅助层（16）。然后通过第一电极将保护层和辅助层（16）打开（17）。然后，制造电介质层（6），然后将用于第二电极的金属轨道堆叠（7,8,9）施加到电介质层（6）。然后使用已知的蚀刻工艺对金属 - 绝缘体 - 金属电容器进行图案化。这使得可以使用可以根据需要选择的材料来制造任何所需厚度的介电电容器层。特别地，这具有以下优点：通过蚀刻可以比现有技术更容易地进行蚀刻，因为不需要通过金属轨道上方的残留介电电容器层进行蚀刻。

6. 发明授权

US06940720B2 Integrated circuit having a thermally shielded electric resistor trace 有权
标题翻译：具有热屏蔽电阻迹的集成电路
公开(公告)号：US06940720B2
公开(公告)日：2005-09-06
申请号：US10424016
申请日：2003-04-25
申请人： Armin Fischer , Johann Helneder , Heinrich Körner , Markus Schwerd , Wolfgang Walter , Alexander Von Glasow
发明人： Armin Fischer , Johann Helneder , Heinrich Körner , Markus Schwerd , Wolfgang Walter , Alexander Von Glasow
IPC分类号： H01L27/08 , H05K7/20
CPC分类号： H01L27/0802
摘要： An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.
摘要翻译：集成电路包括电阻迹线，衬底和布置在电阻迹线上方或下方的导热结构，用于从电阻迹线散热到衬底。本发明基于这样的发现，即通过引入额外的导热结构，尽管由于对基板的导热性显着增加，首先引入了这种额外的导热结构需要空间，但是用于实现集成可以获得电阻。

7. 发明授权

US08367514B2 Integrated circuit with capacitor and method for the production thereof 有权
标题翻译：具有电容器的集成电路及其制造方法
公开(公告)号：US08367514B2
公开(公告)日：2013-02-05
申请号：US12696811
申请日：2010-01-29
申请人： Thomas Goebel , Johann Helneder , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck , Holger Torwesten
发明人： Thomas Goebel , Johann Helneder , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck , Holger Torwesten
IPC分类号： H01L21/302
CPC分类号： H01L28/40 , H01L21/31687 , H01L23/5223 , H01L23/5228 , H01L27/016 , H01L27/0802 , H01L27/0805 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.
摘要翻译：提出了一种集成电路和制造方法。集成电路包括在基极和覆盖电极之间包含基极，覆盖电极和电介质的电容器。电介质包含可以通过阳极氧化产生的基极中包含的材料的氧化物。电介质的外围边缘被覆盖电极覆盖。电容器上的基极层包括与电介质相邻的切口。在制造过程中，基层保护待化学物质被阳极氧化的基底材料，并且保护周围区域免受阳极氧化。可以与电容器同时制造精密电阻器。

8. 发明授权

US07692266B2 Integrated circuit with capacitor and method for the production thereof 有权
标题翻译：具有电容器的集成电路及其生产方法
公开(公告)号：US07692266B2
公开(公告)日：2010-04-06
申请号：US11368254
申请日：2006-03-03
申请人： Thomas Goebel , Johann Helneder , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck , Holger Torwesten
发明人： Thomas Goebel , Johann Helneder , Heinrich Körner , Andrea Mitchell , Markus Schwerd , Martin Seck , Holger Torwesten
IPC分类号： H01L29/43
CPC分类号： H01L28/40 , H01L21/31687 , H01L23/5223 , H01L23/5228 , H01L27/016 , H01L27/0802 , H01L27/0805 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.
摘要翻译：提出了一种集成电路和制造方法。集成电路包括在基极和覆盖电极之间包含基极，覆盖电极和电介质的电容器。电介质包含可以通过阳极氧化产生的基极中包含的材料的氧化物。电介质的外围边缘被覆盖电极覆盖。电容器上的基极层包括与电介质相邻的切口。在制造过程中，基层保护待化学物质被阳极氧化的基底材料，并且保护周围区域免受阳极氧化。可以与电容器同时制造精密电阻器。

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