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1. 发明申请

US20120049951A1 HIGH SPEED SWITCHED CAPACITOR REFERENCE BUFFER 审中-公开
标题翻译：高速开关电容参考缓冲器
公开(公告)号：US20120049951A1
公开(公告)日：2012-03-01
申请号：US12901877
申请日：2010-10-11
申请人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Ganesh Kiran
发明人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Ganesh Kiran
IPC分类号： H03F1/00
CPC分类号： H03F3/505 , G11C27/026 , H03F2203/5018
摘要： Conventional single-ended and differential reference buffers used for switched capacitor loads (such as sample-and-hold circuits for analog-to-digital converters) often have errors due to “memory” and are current source limited. Here, however, single-ended and differential reference buffers are provided, which include low bandwidth switched capacitor feedback loops to limit noise from the feedback loop and decouple internal bias nodes to avoid memory issues. Additionally, the differential reference buffers shown include flipped voltage followers that can sink/source large currents, which are not current source limited, and that can be underdamped so as to obtain a two pole settling response to reduce power consumption.
摘要翻译：用于开关电容器负载的传统单端和差分参考缓冲器（例如模数转换器的采样和保持电路）通常由于“存储器”而导致错误，并且电流源受限。然而，这里提供了单端和差分参考缓冲器，其包括低带宽开关电容器反馈回路，以限制来自反馈回路的噪声并且去耦内部偏置节点以避免存储器问题。此外，所示的差分参考缓冲器包括可以吸收/源极大电流的翻转电压跟随器，其不是电流源限制的，并且可以被阻尼，以获得两极稳定响应以降低功耗。

2. 发明授权

US07948410B2 Multibit recyclic pipelined ADC architecture 有权
标题翻译：多位循环流水线ADC结构
公开(公告)号：US07948410B2
公开(公告)日：2011-05-24
申请号：US12639705
申请日：2009-12-16
申请人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
发明人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
IPC分类号： H03M1/00
CPC分类号： H03M1/0695 , H03M1/167
摘要： An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.
摘要翻译：提供了一种装置。该装置包括采样开关，采样电容器，放大器，反馈分支，第二保持开关，N位转换器对，第三保持开关和M位转换器对。样本接收输入信号并由样本信号启动。采样电容器耦合到采样开关。放大器具有耦合到采样电容器的第一输入端。反馈支路耦合在放大器的输出端和放大器的第一输入端之间，每个反馈支路包括反馈电容器，以及耦合到反馈电容器的第一保持开关。第二保持开关耦合到采样开关。 N位转换器对耦合到采样开关和第二保持开关。第三保持开关耦合到至少一个反馈支路，并且M位转换器对耦合到放大器的输出端和第三保持开关。

3. 发明申请

US20110012764A1 MULTIBIT RECYCLIC PIPELINED ADC ARCHITECTURE 有权
标题翻译：多重循环管道ADC架构
公开(公告)号：US20110012764A1
公开(公告)日：2011-01-20
申请号：US12639705
申请日：2009-12-16
申请人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
发明人： Jagannathan Venkataraman , Visvesvaraya A. Pentakota , Sandeep K. Oswal , Samarth S. Modi , Shagun Dusad
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/0695 , H03M1/167
摘要： An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.
摘要翻译：提供了一种装置。该装置包括采样开关，采样电容器，放大器，反馈分支，第二保持开关，N位转换器对，第三保持开关和M位转换器对。样本接收输入信号并由样本信号启动。采样电容器耦合到采样开关。放大器具有耦合到采样电容器的第一输入端。反馈支路耦合在放大器的输出端和放大器的第一输入端之间，每个反馈支路包括反馈电容器，以及耦合到反馈电容器的第一保持开关。第二保持开关耦合到采样开关。 N位转换器对耦合到采样开关和第二保持开关。第三保持开关耦合到至少一个反馈支路，并且M位转换器对耦合到放大器的输出端和第三保持开关。

4. 发明授权

US07898446B2 Correction of sampling mismatch in time-interleaved analog-to-digital converters 有权
标题翻译：时间交错模数转换器中采样失配的校正
公开(公告)号：US07898446B2
公开(公告)日：2011-03-01
申请号：US12502569
申请日：2009-07-14
申请人： Viswanathan Nagarajan , Visvesvaraya A. Pentakota , Jagannathan Venkataraman
发明人： Viswanathan Nagarajan , Visvesvaraya A. Pentakota , Jagannathan Venkataraman
IPC分类号： H03M1/06
CPC分类号： H03M1/0624 , H03M1/1215
摘要： A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.
摘要翻译：提供了时间交织的模数转换器（ADC）。 ADC通常包括第一ADC，第二ADC，校正电路，分频器和时钟电路。第一ADC接收模拟输入信号并产生第一输出和微分输出。第二个ADC接收模拟输入信号并产生第二个输出。校正电路接收第一输出，第二输出和微分输出，并产生第一误差信号和第二误差信号。分频器接收第一误差信号和第二误差信号，并通过将第二误差信号除以第一误差信号产生定时误差，并且时钟电路接收时钟信号和定时误差，并产生多个校正时钟信号，其中第一和第二ADC中的每一个接收至少一个时钟信号。

5. 发明申请

US20100309033A1 CORRECTION OF SAMPLING MISMATCH IN TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS 有权
标题翻译：在时间间隔模拟数字转换器中采样误差校正的校正
公开(公告)号：US20100309033A1
公开(公告)日：2010-12-09
申请号：US12502569
申请日：2009-07-14
申请人： Viswanathan Nagarajan , Visvesvaraya A. Pentakota , Jagannathan Venkataraman
发明人： Viswanathan Nagarajan , Visvesvaraya A. Pentakota , Jagannathan Venkataraman
IPC分类号： H03M1/06
CPC分类号： H03M1/0624 , H03M1/1215
摘要： A time-interleaved analog-to-digital converter (ADC) is provided. The ADC generally comprises a first ADC, a second ADC, correction circuit, a divider, and a clocking circuit. The first ADC receives an analog input signal and generates a first output and a differentiated output. The second ADC receives the analog input signal and generates a second output. The correction circuit receives the first output, the second output, and the differentiated output and generates a first error signal and a second error signal. The divider receives the first error signal and the second error signal and generates a timing error by dividing the second error signal by the first error signal, and the clocking circuit receives a clock signal and the timing error and generates a plurality of corrected clocking signals, where each of the first and second ADCs receives at least one of the clocking signals.
摘要翻译：提供了时间交织的模数转换器（ADC）。 ADC通常包括第一ADC，第二ADC，校正电路，分频器和时钟电路。第一ADC接收模拟输入信号并产生第一输出和微分输出。第二个ADC接收模拟输入信号并产生第二个输出。校正电路接收第一输出，第二输出和微分输出，并产生第一误差信号和第二误差信号。分频器接收第一误差信号和第二误差信号，并通过将第二误差信号除以第一误差信号产生定时误差，并且时钟电路接收时钟信号和定时误差，并产生多个校正时钟信号，其中第一和第二ADC中的每一个接收至少一个时钟信号。

6. 发明授权

US06891486B1 Calibrating capacitor mismatch in a pipeline ADC 有权
标题翻译：在流水线ADC中校准电容器失配
公开(公告)号：US06891486B1
公开(公告)日：2005-05-10
申请号：US10722416
申请日：2003-11-28
申请人： Visvesvaraya A. Pentakota , Jagannathan Venkataraman , Vineet Mishra
发明人： Visvesvaraya A. Pentakota , Jagannathan Venkataraman , Vineet Mishra
IPC分类号： H03M1/10 , H03M1/16 , H04L20060101
CPC分类号： H03M1/109 , H03M1/168
摘要： An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to sample an input signal and a feedback capacitor (in combination with an amplifier) for amplification. The measured values can be used to generate accurate digital codes representing analog signal samples. The calibration circuit connects the capacitors to various voltage levels and measures the mismatch levels by examining various signals (e.g., the digital codes) generated in such situations.
摘要翻译：可以动态地（即在操作环境中）的片上校准电路使用采样电容器测量ADC中的电容器失配，以对放大的输入信号和反馈电容器（与放大器组合）进行采样。测量值可用于产生表示模拟信号样本的精确数字代码。校准电路将电容器连接到各种电压电平，并通过检查在这种情况下产生的各种信号（例如，数字代码）来测量失配水平。

7. 发明申请

US20080036632A1 SIGNAL-TO-NOISE RATIO WHEN USING FEWER BITS THAN THE NUMBER OF OUTPUT BITS OF AN ANALOG TO DIGITAL CONVERTER 有权
标题翻译：当使用更少的位数比模拟数字转换器的输出位数多的信号噪声比
公开(公告)号：US20080036632A1
公开(公告)日：2008-02-14
申请号：US11836163
申请日：2007-08-09
申请人： Nagarajan Viswanathan , Jagannathan Venkataraman , Ganesh Kiran
发明人： Nagarajan Viswanathan , Jagannathan Venkataraman , Ganesh Kiran
IPC分类号： H03M3/00
CPC分类号： H03M7/3042 , H03M7/3026
摘要： Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of an input signal. In an embodiment, an ADC generates digital values of H bits by sampling an input signal at corresponding time instances. An error signal representing the (H-N) least significant bits of the H-bit digital values is processed to determine respective filtered values, which are respectively added to the corresponding ones of the H-bit digital values. The (H-N) bits of the resulting added values are dropped to generate N bit values. The N bit values thus generated may have improved SNR at least in a band of interest, as desired.
摘要翻译：当使用比ADC的输出位数更少的位作为输入信号样本强度的数字表示时，提高信噪比（SNR）。在一个实施例中，ADC通过在相应的时间实例对输入信号进行采样来产生H位的数字值。处理表示H位数字值的（H-N）最低有效位的错误信号，以确定相应的滤波值，它们分别加到相应的H位数字值中。所产生的相加值的（H-N）位被丢弃以产生N位值。如此产生的N位值至少可以根据需要在感兴趣的频带中具有改善的SNR。

8. 发明授权

US07425911B2 Signal-to-noise ratio when using fewer bits than the number of output bits of an analog to digital converter 有权
标题翻译：当使用比模数转换器的输出位数更少的位时，信噪比
公开(公告)号：US07425911B2
公开(公告)日：2008-09-16
申请号：US11836163
申请日：2007-08-09
申请人： Nagarajan Viswanathan , Jagannathan Venkataraman , Ganesh Kiran
发明人： Nagarajan Viswanathan , Jagannathan Venkataraman , Ganesh Kiran
IPC分类号： H03M3/00
CPC分类号： H03M7/3042 , H03M7/3026
摘要： Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of an input signal. In an embodiment, an ADC generates digital values of H bits by sampling an input signal at corresponding time instances. An error signal representing the (H-N) least significant bits of the H-bit digital values is processed to determine respective filtered values, which are respectively added to the corresponding ones of the H-bit digital values. The (H-N) bits of the resulting added values are dropped to generate N bit values. The N bit values thus generated may have improved SNR at least in a band of interest, as desired.
摘要翻译：当使用比ADC的输出位数更少的位作为输入信号样本强度的数字表示时，提高信噪比（SNR）。在一个实施例中，ADC通过在相应的时间实例对输入信号进行采样来产生H位的数字值。处理表示H位数字值的（H-N）最低有效位的错误信号，以确定相应的滤波值，它们分别加到相应的H位数字值中。所产生的相加值的（H-N）位被丢弃以产生N位值。如此产生的N位值至少可以根据需要在感兴趣的频带中具有改善的SNR。

9. 发明授权

US08847578B2 Ambient noise cancellation in pulsed input system 有权
标题翻译：脉冲输入系统环境噪声消除
公开(公告)号：US08847578B2
公开(公告)日：2014-09-30
申请号：US13553810
申请日：2012-07-19
申请人： Jagannathan Venkataraman , Sandeep Kesrimai Oswal , Vinod Srinivasan Paliakara
发明人： Jagannathan Venkataraman , Sandeep Kesrimai Oswal , Vinod Srinivasan Paliakara
IPC分类号： G01R1/30 , H03M3/00 , H03M1/12 , G01R19/25
CPC分类号： H03M1/1295 , G01R19/2506 , H03M3/494
摘要： Embodiments of the invention provide a pulseoximetry system with ambient offset cancellation that subtracts an estimated ambient offset to thereby allow a large front end gain while operating the front end on a low supply voltage. This large gain reduces input referred noise of an analog to digital converter in the front end while providing high dynamic range for signals with a large ambient offset.
摘要翻译：本发明的实施例提供了一种具有环境偏移消除的脉搏摄像系统，其减去估计的环境偏移，从而在低电源电压下操作前端时允许较大的前端增益。这种大的增益降低了前端的模数转换器的输入参考噪声，同时为具有大的环境偏移的信号提供了高动态范围。

10. 发明申请

US20100080083A1 Time-Dependant Gain Control For An Amplifier Used In Receiving Echoes 有权
标题翻译：用于接收回波的放大器的时间依赖增益控制
公开(公告)号：US20100080083A1
公开(公告)日：2010-04-01
申请号：US12241075
申请日：2008-09-30
申请人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
发明人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
IPC分类号： G01S15/00
CPC分类号： G01S7/52033
摘要： An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system.
摘要翻译：放大器电路，用于放大回波序列并产生相应的放大信号序列。在一个实施例中，放大器包括具有可变输入和反馈电阻的运算放大器，使得可以控制两个电阻的比率。增益控制块以时间依赖的方式控制比率，以获得每个回波的期望的增益因子。可以预先计算增益因子，使得在超声系统的情况下，所有回波都被获得到相同的水平。

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