专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07394125B1 Recessed channel with separated ONO memory device 有权
标题翻译：嵌入式通道具有分离的ONO存储器件
公开(公告)号：US07394125B1
公开(公告)日：2008-07-01
申请号：US11361277
申请日：2006-02-24
申请人： Jaeyong Park , Hidehiko Shiraiwa , Satoshi Torii , Mark T. Ramsbey
发明人： Jaeyong Park , Hidehiko Shiraiwa , Satoshi Torii , Mark T. Ramsbey
IPC分类号： H01L23/62 , H01L21/336
CPC分类号： H01L29/42352 , H01L27/105 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.
摘要翻译：提供了制造具有凹陷通道和分段/分离的ONO层的U形存储器件的系统和方法。通过分离的ONO层促进多位操作，该ONO层包括邻近源极/漏极区的多晶硅栅极结构的侧壁上的电荷俘获区域。存储器单元的编程和擦除由于作用源极区域和栅极之间的距离相对较短而便于实现。此外，通过在凹陷多晶硅栅极周围移动的相对较长的U形沟道区域减轻了短沟道效应，从而增加了沟道长度的深度尺寸。

2. 发明授权

US07067377B1 Recessed channel with separated ONO memory device 有权
标题翻译：嵌入式通道具有分离的ONO存储器件
公开(公告)号：US07067377B1
公开(公告)日：2006-06-27
申请号：US10812703
申请日：2004-03-30
申请人： Jaeyong Park , Hidehiko Shiraiwa , Satoshi Torii , Mark T. Ramsbey
发明人： Jaeyong Park , Hidehiko Shiraiwa , Satoshi Torii , Mark T. Ramsbey
IPC分类号： H01L21/336
CPC分类号： H01L29/42352 , H01L27/105 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.
摘要翻译：提供了制造具有凹陷通道和分段/分离的ONO层的U形存储器件的系统和方法。通过分离的ONO层促进多位操作，该ONO层包括邻近源极/漏极区的多晶硅栅极结构的侧壁上的电荷俘获区域。存储器单元的编程和擦除由于作用源极区域和栅极之间的距离相对较短而便于实现。此外，通过在凹陷多晶硅栅极周围移动的相对较长的U形沟道区域减轻了短沟道效应，从而增加了沟道长度的深度尺寸。

3. 发明授权

US07692236B1 Multiple dual bit memory integrated circuit system 有权
标题翻译：多重双位存储器集成电路系统
公开(公告)号：US07692236B1
公开(公告)日：2010-04-06
申请号：US11059139
申请日：2005-02-15
申请人： Michael Brennan , Jaeyong Park , Hidehiko Shiraiwa , Satoshi Torii
发明人： Michael Brennan , Jaeyong Park , Hidehiko Shiraiwa , Satoshi Torii
IPC分类号： H01L23/62
CPC分类号： H01L29/66833 , H01L27/11568 , H01L27/11578 , H01L29/7923
摘要： A multiple dual bit integrated circuit system is provided that includes forming first address lines in a semiconductor substrate and forming a charge-trapping layer over the semiconductor substrate. A semiconductor layer is formed over the charge-trapping layer and second address lines are formed in the semiconductor layer to form a plurality of dual bit locations.
摘要翻译：提供了一种多重双位集成电路系统，其包括在半导体衬底中形成第一地址线并在半导体衬底上形成电荷捕获层。在电荷俘获层上形成半导体层，并且在半导体层中形成第二地址线以形成多个双位位置。

4. 发明授权

US07196008B1 Aluminum oxide as liner or cover layer to spacers in memory device 有权
标题翻译：氧化铝作为衬垫或覆盖层与存储器件中的间隔物
公开(公告)号：US07196008B1
公开(公告)日：2007-03-27
申请号：US11087793
申请日：2005-03-23
申请人： Hidehiko Shiraiwa , Satoshi Torii , Jaeyong Park , Joong Jeon
发明人： Hidehiko Shiraiwa , Satoshi Torii , Jaeyong Park , Joong Jeon
IPC分类号： H01L21/44
CPC分类号： H01L21/76829 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of Al2O3 for example. Such aluminum oxide may be used as an etch stop layer in a periphery region, a metal silicide block, and a hydrogen block for enhanced performance of the memory device.
摘要翻译：为了制造存储器件，在字线栅极的侧面形成间隔物。此外，氧化铝形成为间隔物的衬垫层或覆盖层之一。氧化铝具有例如Al 2 O 3 N 3的化学组成。这种氧化铝可以用作外围区域中的蚀刻停止层，金属硅化物块和氢块，以增强存储器件的性能。

5. 发明申请

US20070058442A1 SONOS memory with inversion bit-lines 有权
标题翻译：具有反转位线的SONOS存储器
公开(公告)号：US20070058442A1
公开(公告)日：2007-03-15
申请号：US11595639
申请日：2006-11-10
申请人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
发明人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
IPC分类号： G11C16/04
CPC分类号： H01L29/792 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.
摘要翻译：形成在半导体衬底内的SONOS存储单元包括设置在半导体衬底上的底部电介质，设置在底部电介质上的电荷捕获材料和设置在电荷俘获材料上的顶部电介质。此外，SONOS存储单元包括设置在顶部电介质上的字线栅极结构和用于在半导体衬底内引入至少一个反转位线的至少一个位线栅极。

6. 发明授权

US07151293B1 SONOS memory with inversion bit-lines 有权
公开(公告)号：US07151293B1
公开(公告)日：2006-12-19
申请号：US10928582
申请日：2004-08-27
申请人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
发明人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
IPC分类号： H01L29/72
CPC分类号： H01L29/792 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

7. 发明授权

US07501677B2 SONOS memory with inversion bit-lines 有权
标题翻译：具有反转位线的SONOS存储器
公开(公告)号：US07501677B2
公开(公告)日：2009-03-10
申请号：US11595639
申请日：2006-11-10
申请人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
发明人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
IPC分类号： H01L29/72
CPC分类号： H01L29/792 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.
摘要翻译：形成在半导体衬底内的SONOS存储单元包括设置在半导体衬底上的底部电介质，设置在底部电介质上的电荷捕获材料和设置在电荷俘获材料上的顶部电介质。此外，SONOS存储单元包括设置在顶部电介质上的字线栅极结构和用于在半导体衬底内引入至少一个反转位线的至少一个位线栅极。

8. 发明授权

US07416940B1 Methods for fabricating flash memory devices 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US07416940B1
公开(公告)日：2008-08-26
申请号：US11418352
申请日：2006-05-03
申请人： Satoshi Torii , Hidehiko Shiraiwa , Youseok Suh , Lei Xue
发明人： Satoshi Torii , Hidehiko Shiraiwa , Youseok Suh , Lei Xue
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.
摘要翻译：提供了制造闪速存储器件的方法。一种方法包括形成覆盖衬底的多个栅叠层。每个栅极堆叠包括电荷捕获层和控制栅极。控制栅极是离基板的第一距离。相邻的门堆叠是第二个距离。沉积电池间隔物材料层并被蚀刻以形成围绕每个栅极叠层的侧壁的间隔物。在第一栅极堆叠和最后一个栅极堆叠附近形成源极/漏极杂质掺杂区域。第一距离和第二距离使得当在读取操作期间将电压施加到栅极堆叠时，在栅极堆叠的控制栅极和衬底之间产生边缘场，并且足以将一部分栅极堆叠和相邻栅极堆叠之间的衬底。

9. 发明授权

US07675104B2 Integrated circuit memory system employing silicon rich layers 有权
标题翻译：集成电路存储系统采用富硅层
公开(公告)号：US07675104B2
公开(公告)日：2010-03-09
申请号：US11461131
申请日：2006-07-31
申请人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
发明人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L21/3081 , H01L21/76224 , H01L27/115 , H01L29/66833
摘要： An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.
摘要翻译：一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

10. 发明申请

US20080121981A1 MEMORY SYSTEM WITH PROTECTION LAYER TO COVER THE MEMORY GATE STACK AND METHODS FOR FORMING SAME 有权
标题翻译：具有保护层的存储器系统，以覆盖存储器栅极堆叠及其形成方法
公开(公告)号：US20080121981A1
公开(公告)日：2008-05-29
申请号：US11469164
申请日：2006-08-31
申请人： Hidehiko Shiraiwa , YouSeok Suh , Harpreet Sachar , Satoshi Torii
发明人： Hidehiko Shiraiwa , YouSeok Suh , Harpreet Sachar , Satoshi Torii
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568
摘要： A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.
摘要翻译：提供了一种存储器系统，包括形成在半导体衬底上具有电荷陷阱层的存储器栅极堆叠，形成覆盖存储器栅极堆叠的保护层，以及形成用于具有保护层和存储栅极的电荷陷阱层的保护外壳堆栈

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式