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1. 发明申请

US20060113599A1 Semiconductor devices having self-aligned bodies and methods of forming the same 审中-公开
标题翻译：具有自对准体的半导体器件及其形成方法
公开(公告)号：US20060113599A1
公开(公告)日：2006-06-01
申请号：US11233415
申请日：2005-09-22
申请人： Jae-Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
发明人： Jae-Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/783 , H01L29/78606 , H01L29/78654
摘要： A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.
摘要翻译：半导体器件包括具有源极区域，漏极区域，插入在源极区域和漏极区域之间的沟道区域的主体区域以及从沟道区域的端部延伸的主体区域延伸部。在沟道区域和体区域上形成栅极图案，并且体接触将栅极图案连接到身体区域。身体区域延伸部的侧壁与栅极图案的侧壁自对准。还公开了具有自对准体和身体接触的半导体器件的形成方法。

2. 发明授权

US08084306B2 Methods of forming semiconductor devices having self-aligned bodies 失效
标题翻译：形成具有自对准体的半导体器件的方法
公开(公告)号：US08084306B2
公开(公告)日：2011-12-27
申请号：US12409968
申请日：2009-03-24
申请人： Jae-Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
发明人： Jae-Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/783 , H01L29/78606 , H01L29/78654
摘要： A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.
摘要翻译：半导体器件包括具有源极区域，漏极区域，插入在源极区域和漏极区域之间的沟道区域的主体区域以及从沟道区域的端部延伸的主体区域延伸部。在沟道区域和体区域上形成栅极图案，并且体接触将栅极图案连接到身体区域。身体区域延伸部的侧壁与栅极图案的侧壁自对准。还公开了具有自对准体和身体接触的半导体器件的形成方法。

3. 发明申请

US20090181511A1 METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED BODIES 失效
标题翻译：形成具有自对准体的半导体器件的方法
公开(公告)号：US20090181511A1
公开(公告)日：2009-07-16
申请号：US12409968
申请日：2009-03-24
申请人： Jae Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
发明人： Jae Hun Jeong , Hoon Lim , Soon-Moon Jung , Hoo-Sung Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/783 , H01L29/78606 , H01L29/78654
摘要： A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.
摘要翻译：半导体器件包括具有源极区域，漏极区域，插入在源极区域和漏极区域之间的沟道区域的主体区域以及从沟道区域的端部延伸的主体区域延伸部。在沟道区域和体区域上形成栅极图案，并且体接触将栅极图案连接到身体区域。身体区域延伸部的侧壁与栅极图案的侧壁自对准。还公开了具有自对准体和身体接触的半导体器件的形成方法。

4. 发明申请

US20090233405A1 METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES 有权
标题翻译：形成NAND型非易失性存储器件的方法
公开(公告)号：US20090233405A1
公开(公告)日：2009-09-17
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

5. 发明授权

US07554140B2 Nand-type non-volatile memory device 失效
标题翻译： Nand型非易失性存储器件
公开(公告)号：US07554140B2
公开(公告)日：2009-06-30
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L31/062
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

6. 发明授权

US08258517B2 Semiconductor device having driving transistors 有权
标题翻译：具有驱动晶体管的半导体器件
公开(公告)号：US08258517B2
公开(公告)日：2012-09-04
申请号：US12473055
申请日：2009-05-27
申请人： Jong-In Yun , Soon-Moon Jung , Han-Soo Kim , Hoo-Sung Cho , Jun-Beom Park , Jae-Hun Jeong
发明人： Jong-In Yun , Soon-Moon Jung , Han-Soo Kim , Hoo-Sung Cho , Jun-Beom Park , Jae-Hun Jeong
IPC分类号： H01L29/08
CPC分类号： H01L21/76224 , H01L21/8221 , H01L27/0688 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion.
摘要翻译：本文示例性描述的一个实施方案通常可以表征为半导体器件，其包括位于半导体衬底上方的较低级器件层，位于下级器件层上的层间绝缘膜和位于层间绝缘膜上方的上位器件层。下层器件层可以包括形成在衬底中的多个器件。上级器件层可以包括多个半导体图案和形成在多个半导体图案中的每一个中的至少一个器件。多个半导体图案可以彼此电隔离。多个半导体图案中的每一个可以包括至少一个有效部分和至少一个电连接到该至少一个有效部分的主体接触部分。

7. 发明授权

US07701771B2 Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same 有权
标题翻译：包括三维布置的存储单元晶体管的存储器件及其操作方法
公开(公告)号：US07701771B2
公开(公告)日：2010-04-20
申请号：US11882769
申请日：2007-08-06
申请人： Jae-Hun Jeong , Ki-Nam Kim , Soon-Moon Jung , Hoo-Sung Cho
发明人： Jae-Hun Jeong , Ki-Nam Kim , Soon-Moon Jung , Hoo-Sung Cho
IPC分类号： G11C11/03
CPC分类号： H01L27/115 , H01L21/8221 , H01L27/0688 , H01L27/11521 , H01L27/11524 , H01L27/11551
摘要： A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.
摘要翻译：存储器件可以包括L个半导体层，每个半导体层上的栅极结构，N个位线和/或每个半导体层上的公共源极线。 L个半导体层可以被堆叠，和/或L可以是大于1的整数.N个位线可以在栅极结构上并且跨过栅极结构，和/或N可以是大于1的整数。公共源极线可以彼此连接，使得公共源极线彼此具有等电位。

8. 发明申请

US20080085582A1 Hand-type nonvolatile memory device and method of forming the same 失效
标题翻译：手持式非易失性存储装置及其形成方法
公开(公告)号：US20080085582A1
公开(公告)日：2008-04-10
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

9. 发明授权

US07709323B2 Methods of forming nand-type nonvolatile memory devices 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US07709323B2
公开(公告)日：2010-05-04
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

10. 发明授权

US07646664B2 Semiconductor device with three-dimensional array structure 有权
标题翻译：具有三维阵列结构的半导体器件
公开(公告)号：US07646664B2
公开(公告)日：2010-01-12
申请号：US11869140
申请日：2007-10-09
申请人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
发明人： Hoo-Sung Cho , Soon-Moon Jung , Young-Seop Rah , Jae-Hoon Jang , Jae-Hun Jeong , Jun-Beom Park
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C8/14 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11568
摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.
摘要翻译：一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线，并且第一字线可以在第一和第二半导体层之间。第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

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