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1. 发明申请

US20090233405A1 METHODS OF FORMING NAND-TYPE NONVOLATILE MEMORY DEVICES 有权
标题翻译：形成NAND型非易失性存储器件的方法
公开(公告)号：US20090233405A1
公开(公告)日：2009-09-17
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

2. 发明授权

US07554140B2 Nand-type non-volatile memory device 失效
标题翻译： Nand型非易失性存储器件
公开(公告)号：US07554140B2
公开(公告)日：2009-06-30
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L31/062
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

3. 发明申请

US20080085582A1 Hand-type nonvolatile memory device and method of forming the same 失效
标题翻译：手持式非易失性存储装置及其形成方法
公开(公告)号：US20080085582A1
公开(公告)日：2008-04-10
申请号：US11651892
申请日：2007-01-10
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.
摘要翻译：提供了一种NAND型非易失性存储器件及其形成方法。在该方法中，多个单元层层叠在半导体基板上。用于形成包含在层叠电池中的半导体图案的种子接触孔以规则的距离形成。此时，种子接触孔布置成使得位线插头或源极线图案设置在彼此相邻的一对种子接触孔之间的中心处。

4. 发明授权

US07709323B2 Methods of forming nand-type nonvolatile memory devices 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US07709323B2
公开(公告)日：2010-05-04
申请号：US12474896
申请日：2009-05-29
申请人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
发明人： Hoo-Sung Cho , Soon-Moon Jung , Won-Seok Cho , Jong-Hyuk Kim , Jae-Hun Jeong , Jae-Hoon Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , H01L27/0688 , H01L27/11551
摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.
摘要翻译：形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层半导体衬底的整个表面使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

5. 发明授权

US07683404B2 Stacked memory and method for forming the same 有权
标题翻译：堆积记忆及其形成方法
公开(公告)号：US07683404B2
公开(公告)日：2010-03-23
申请号：US11709234
申请日：2007-02-22
申请人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Hoo-Sung Cho , Jong-Hyuk Kim
发明人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Hoo-Sung Cho , Jong-Hyuk Kim
IPC分类号： H01L25/065
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.
摘要翻译：堆叠存储器包括至少两个半导体层，每个半导体层包括存储单元阵列。晶体管形成在至少两个半导体层的最上半导体层的外围电路区域中。晶体管用于操作存储单元阵列。

6. 发明申请

US20080067573A1 Stacked memory and method for forming the same 有权
标题翻译：堆积记忆及其形成方法
公开(公告)号：US20080067573A1
公开(公告)日：2008-03-20
申请号：US11709234
申请日：2007-02-22
申请人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Hoo-Sung Cho , Jong-Hyuk Kim
发明人： Young-Chul Jang , Won-Seok Cho , Jae-Hoon Jang , Soon-Moon Jung , Hoo-Sung Cho , Jong-Hyuk Kim
IPC分类号： H01L29/788
CPC分类号： H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/11551
摘要： A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.
摘要翻译：堆叠存储器包括至少两个半导体层，每个半导体层包括存储单元阵列。晶体管形成在至少两个半导体层的最上半导体层的外围电路区域中。晶体管用于操作存储单元阵列。

7. 发明授权

US07719033B2 Semiconductor devices having thin film transistors and methods of fabricating the same 有权
标题翻译：具有薄膜晶体管的半导体器件及其制造方法
公开(公告)号：US07719033B2
公开(公告)日：2010-05-18
申请号：US11364773
申请日：2006-02-28
申请人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
发明人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
IPC分类号： H01L29/74
CPC分类号： H01L27/0688 , H01L23/485 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.
摘要翻译：提供具有薄膜晶体管（TFT）的半导体器件及其制造方法。半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。下部半导体本体设置在下部层间绝缘层上或下部层间绝缘层中。下部TFT包括设置在下部半导体本体中的下部源极区域和下部漏极区域以及下部栅极电极，该下部栅极电极覆盖并交叉配置在下部半导体本体的下侧半导体本体的至少两个表面的至少一部分源极和漏极区域。

8. 发明申请

US20060237725A1 Semiconductor devices having thin film transistors and methods of fabricating the same 有权
标题翻译：具有薄膜晶体管的半导体器件及其制造方法
公开(公告)号：US20060237725A1
公开(公告)日：2006-10-26
申请号：US11364773
申请日：2006-02-28
申请人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
发明人： Jae-Hun Jeong , Soon-Moon Jung , Hoon Lim , Won-Seok Cho , Jin-Ho Kim , Chang-Min Hong , Jong-Hyuk Kim , Kun-Ho Kwak
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L27/0688 , H01L23/485 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.
摘要翻译：提供具有薄膜晶体管（TFT）的半导体器件及其制造方法。半导体器件包括设置在半导体衬底上的半导体衬底和下层间绝缘层。下部半导体本体设置在下部层间绝缘层上或下部层间绝缘层中。下部TFT包括设置在下部半导体本体中的下部源极区域和下部漏极区域以及下部栅极电极，该下部栅极电极覆盖并交叉配置在下部半导体器件的下部半导体本体的至少两个表面的至少一部分源极和漏极区域。

9. 发明申请

US20060097319A1 Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby 有权
标题翻译：在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件
公开(公告)号：US20060097319A1
公开(公告)日：2006-05-11
申请号：US11197836
申请日：2005-08-05
申请人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
发明人： Jong-Hyuk Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Sung-Jin Kim , Jae-Joo Shim
IPC分类号： H01L27/01
CPC分类号： H01L21/8221 , H01L21/28525 , H01L21/76877 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/12 , H01L29/785
摘要： Methods of forming a single crystal semiconductor thin film on an insulator and semiconductor devices fabricated thereby are provided. The methods include forming an interlayer insulating layer on a single crystal semiconductor layer. A single crystal semiconductor plug is formed to penetrate the interlayer insulating layer. A semiconductor oxide layer is formed within the single crystal semiconductor plug using an ion implantation technique and an annealing technique. As a result, the single crystal semiconductor plug is divided into a lower plug and an upper single crystal semiconductor plug with the semiconductor oxide layer being interposed therebetween. That is, the upper single crystal semiconductor plug is electrically insulated from the lower plug by the semiconductor oxide layer. A single crystal semiconductor pattern is formed to be in contact with the upper single crystal semiconductor plug and cover the interlayer insulating layer. The single crystal semiconductor pattern is grown by an epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer, or by a solid epitaxy growth technique using the upper single crystal semiconductor plug as a seed layer.
摘要翻译：提供了在绝缘体上形成单晶半导体薄膜的方法和由此制造的半导体器件。所述方法包括在单晶半导体层上形成层间绝缘层。形成单晶半导体插塞以穿透层间绝缘层。使用离子注入技术和退火技术在单晶半导体插头内形成半导体氧化物层。结果，单晶半导体插头被分成下插头和上部单晶半导体插头，半导体氧化物层之间插入其中。也就是说，上单晶半导体插头通过半导体氧化物层与下插塞电绝缘。单晶半导体图案形成为与上单晶半导体插头接触并覆盖层间绝缘层。通过使用上部单晶半导体插塞作为种子层的外延生长技术，或通过使用上部单晶半导体插塞作为种子层的固体外延生长技术，生长单晶半导体图案。

10. 发明授权

US07276404B2 Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns 有权
公开(公告)号：US07276404B2
公开(公告)日：2007-10-02
申请号：US11589618
申请日：2006-10-30
申请人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
发明人： Sung-Jin Kim , Soon-Moon Jung , Won-Seok Cho , Jae-Hoon Jang , Kun-Ho Kwak , Jong-Hyuk Kim , Jae-Joo Shim
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1108 , Y10S257/903
摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

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