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1. 发明申请

US20100156457A1 PLD PROVIDING SOFT WAKEUP LOGIC 有权
标题翻译： PLD提供软件唤醒逻辑
公开(公告)号：US20100156457A1
公开(公告)日：2010-06-24
申请号：US12340358
申请日：2008-12-19
申请人： Jonathan W. Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
发明人： Jonathan W. Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
IPC分类号： H03K19/177 , H03K19/0175
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译：公开了具有多个可编程区域的可编程逻辑器件（PLD）。一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

2. 发明授权

US07884640B2 PLD providing soft wakeup logic 有权
标题翻译： PLD提供软唤醒逻辑
公开(公告)号：US07884640B2
公开(公告)日：2011-02-08
申请号：US12340358
申请日：2008-12-19
申请人： Jonathan W Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
发明人： Jonathan W Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
IPC分类号： H03K19/173
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译：公开了具有多个可编程区域的可编程逻辑器件（PLD）。一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

3. 发明授权

US07522453B1 Non-volatile memory with source-side column select 有权
标题翻译：源极列选择非易失性存储器
公开(公告)号：US07522453B1
公开(公告)日：2009-04-21
申请号：US11961134
申请日：2007-12-20
申请人： Zhigang Wang , Gregory Bakker , Volker Hecht , Santosh Yachareni , Fethi Dhaoui , Vidyadhara Bellippady
发明人： Zhigang Wang , Gregory Bakker , Volker Hecht , Santosh Yachareni , Fethi Dhaoui , Vidyadhara Bellippady
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/08
摘要： A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the odd and even source lines, sources coupled to ground, and gates coupled to a segment-select line. A plurality of odd non-volatile memory transistors each has a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate. A plurality of even non-volatile memory transistors, each has a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate. The control gate of each even non-volatile memory transistor is coupled to the control gate of a different one of the odd non-volatile memory transistors.
摘要翻译：非易失性存储器阵列段包括具有耦合到奇数源极线的漏极和耦合到偶数源极线的漏极的偶数选择晶体管的奇数选择晶体管。两个段选择晶体管具有耦合到奇数和偶数源极线的不同源极，耦合到地的源极和耦合到段选择线的栅极的漏极。多个奇数非易失性存储晶体管各自具有耦合到公共漏极线的漏极，耦合到奇数源极线的源极，浮动栅极和控制栅极。多个偶数非易失性存储晶体管每个都具有耦合到公共漏极线的漏极，耦合到偶数源极线的源极，浮动栅极和控制栅极。每个偶数非易失性存储晶体管的控制栅极耦合到奇数非易失性存储晶体管中不同一个的控制栅极。

4. 发明授权

US07919977B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07919977B2
公开(公告)日：2011-04-05
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

5. 发明授权

US07804321B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07804321B2
公开(公告)日：2010-09-28
申请号：US12205656
申请日：2008-09-05
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

6. 发明申请

US20100315118A1 CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES 有权
标题翻译：用于测试FPGA路由开关的电路和方法
公开(公告)号：US20100315118A1
公开(公告)日：2010-12-16
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

7. 发明授权

US07816946B1 Inverting flip-flop for use in field programmable gate arrays 有权
标题翻译：用于现场可编程门阵列的反相触发器
公开(公告)号：US07816946B1
公开(公告)日：2010-10-19
申请号：US12360948
申请日：2009-01-28
申请人： Volker Hecht , Fei Li , Jonathan W. Greene
发明人： Volker Hecht , Fei Li , Jonathan W. Greene
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1778
摘要： A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
摘要翻译：公开了一种用于现场可编程门阵列集成电路器件的触发器。触发器包括耦合到第一可编程路由元件的数据输出端子，耦合到第二可编程路由元件的数据输入端子和时钟输入端子，其中响应于施加的信号在数据输出端子出现的信号时钟输入端子相对于施加到数据输入端子的相应逻辑信号具有相反的逻辑极性。

8. 发明授权

US07932745B2 Inverting flip-flop for use in field programmable gate arrays 有权
标题翻译：用于现场可编程门阵列的反相触发器
公开(公告)号：US07932745B2
公开(公告)日：2011-04-26
申请号：US12879306
申请日：2010-09-10
申请人： Volker Hecht , Fei Li , Jonathan W. Greene
发明人： Volker Hecht , Fei Li , Jonathan W. Greene
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1778
摘要： A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
摘要翻译：公开了一种用于现场可编程门阵列集成电路器件的触发器。触发器包括耦合到第一可编程路由元件的数据输出端子，耦合到第二可编程路由元件的数据输入端子和时钟输入端子，其中响应于施加的信号在数据输出端子出现的信号时钟输入端子相对于施加到数据输入端子的相应逻辑信号具有相反的逻辑极性。

9. 发明申请

US20100327906A1 INVERTING FLIP-FLOP FOR USE IN FIELD PROGRAMMABLE GATE ARRAYS 有权
标题翻译：用于现场可编程门阵列的反转FLOP FLOP
公开(公告)号：US20100327906A1
公开(公告)日：2010-12-30
申请号：US12879306
申请日：2010-09-10
申请人： Volker Hecht , Fei Li , Jonathan W. Greene
发明人： Volker Hecht , Fei Li , Jonathan W. Greene
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/1778
摘要： A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
摘要翻译：公开了一种用于现场可编程门阵列集成电路器件的触发器。触发器包括耦合到第一可编程路由元件的数据输出端子，耦合到第二可编程路由元件的数据输入端子和时钟输入端子，其中响应于施加的信号在数据输出端子出现的信号时钟输入端子相对于施加到数据输入端子的相应逻辑信号具有相反的逻辑极性。

10. 发明申请

US20100060311A1 CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES 有权
公开(公告)号：US20100060311A1
公开(公告)日：2010-03-11
申请号：US12205656
申请日：2008-09-05
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H03K19/177
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

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