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1. 发明授权

US08244791B1 Fast carry lookahead circuits 有权
标题翻译：快速携带查找电路
公开(公告)号：US08244791B1
公开(公告)日：2012-08-14
申请号：US12022721
申请日：2008-01-30
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

2. 发明授权

US09170774B2 Fast carry lookahead circuits 有权
标题翻译：快速携带查找电路
公开(公告)号：US09170774B2
公开(公告)日：2015-10-27
申请号：US13494850
申请日：2012-06-12
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/508
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

3. 发明申请

US20120259908A1 FAST CARRY LOOKAHEAD CIRCUITS 有权
标题翻译：快速携带LOOKAHEAD电路
公开(公告)号：US20120259908A1
公开(公告)日：2012-10-11
申请号：US13494850
申请日：2012-06-12
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/508
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

4. 发明申请

US20130111119A1 RAM BLOCK DESIGNED FOR EFFICIENT GANGING 有权
标题翻译： RAM块被设计用于高效率
公开(公告)号：US20130111119A1
公开(公告)日：2013-05-02
申请号：US13285210
申请日：2011-10-31
申请人： Volker Hecht , Jonathan Greene
发明人： Volker Hecht , Jonathan Greene
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , H03K19/17768 , H03K19/17796
摘要： A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.
摘要翻译：用于现场可编程门阵列的随机存取存储器块包括具有地址输入，数据输入，数据输出并且包括多个存储位置的随机存取存储器阵列。提供至少两个可编程的可逆可用输入。硬连线解码逻辑被耦合到至少两个可编程的可逆可用使能输入以选择性地启用随机存取存储器阵列。门被耦合到随机存取存储器阵列的输出，并且被配置为仅当对读操作启用随机存取存储器时才传递随机存取存储器阵列的输出，否则生成预选逻辑状态。

5. 发明授权

US08868820B2 RAM block designed for efficient ganging 有权
标题翻译： RAM块设计用于高效组合
公开(公告)号：US08868820B2
公开(公告)日：2014-10-21
申请号：US13285210
申请日：2011-10-31
申请人： Volker Hecht , Jonathan Greene
发明人： Volker Hecht , Jonathan Greene
IPC分类号： G06F12/00 , H03K19/177
CPC分类号： G06F12/00 , H03K19/17768 , H03K19/17796
摘要： A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.
摘要翻译：用于现场可编程门阵列的随机存取存储器块包括具有地址输入，数据输入，数据输出并且包括多个存储位置的随机存取存储器阵列。提供至少两个可编程的可逆可用输入。硬连线解码逻辑被耦合到至少两个可编程的可逆可用使能输入以选择性地启用随机存取存储器阵列。门被耦合到随机存取存储器阵列的输出，并且被配置为仅当对读操作启用随机存取存储器时才传递随机存取存储器阵列的输出，否则生成预选逻辑状态。

6. 发明授权

US07919977B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07919977B2
公开(公告)日：2011-04-05
申请号：US12860004
申请日：2010-08-20
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

7. 发明申请

US20060244485A1 THREE INPUT FIELD PROGRAMMABLE GATE ARRAY LOGIC CIRCUIT CONFIGURABLE AS A THREE INPUT LOOK UP TABLE, A D-LATCH OR A D FLIP-FLOP 失效
标题翻译：三个输入现场可编程门阵列逻辑电路可配置为三个输入查看表，D-LATCH或A D FLIP FLOP
公开(公告)号：US20060244485A1
公开(公告)日：2006-11-02
申请号：US11426158
申请日：2006-06-23
申请人： Alan Reynolds , Andrew Reynolds , Volker Hecht
发明人： Alan Reynolds , Andrew Reynolds , Volker Hecht
IPC分类号： H03K19/177
CPC分类号： H03K19/1733 , H03K19/17728
摘要： A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.
摘要翻译：现场可编程门阵列逻辑单元包括具有三个输入的逻辑电路和至少一个具有输入和输出的输出和多个复用器。逻辑电路还包括耦合在三个输入之间的多个可编程元件和逻辑电路的至少一个输出以及多个多路复用器的输入和输出，使得可以通过编程实现多个顺序逻辑单元和组合单元可选择的可编程元件，顺序逻辑单元可以包括触发器。

8. 发明授权

US07106100B1 Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop 失效
公开(公告)号：US07106100B1
公开(公告)日：2006-09-12
申请号：US10877872
申请日：2004-06-24
申请人： Alan B. Reynolds , Andrew W. Reynolds , Volker Hecht
发明人： Alan B. Reynolds , Andrew W. Reynolds , Volker Hecht
IPC分类号： G06F7/38
CPC分类号： H03K19/1733 , H03K19/17728
摘要： A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

9. 发明授权

US07884640B2 PLD providing soft wakeup logic 有权
标题翻译： PLD提供软唤醒逻辑
公开(公告)号：US07884640B2
公开(公告)日：2011-02-08
申请号：US12340358
申请日：2008-12-19
申请人： Jonathan W Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
发明人： Jonathan W Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
IPC分类号： H03K19/173
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译：公开了具有多个可编程区域的可编程逻辑器件（PLD）。一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

10. 发明授权

US07804321B2 Circuits and methods for testing FPGA routing switches 有权
标题翻译： FPGA路由交换机的电路和方法
公开(公告)号：US07804321B2
公开(公告)日：2010-09-28
申请号：US12205656
申请日：2008-09-05
申请人： Jonathan W. Greene , John McCollum , Volker Hecht
发明人： Jonathan W. Greene , John McCollum , Volker Hecht
IPC分类号： H03K19/00 , H01L25/00
CPC分类号： H03K19/17764 , G01R31/318519 , H03K19/17736
摘要： An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.
摘要翻译： FPGA架构包括具有非易失性开关的多路复用器，其具有耦合到字线W的控制栅极，与行相关联的每个字线，所述开关通过具有可控接地连接NGND的缓冲器连接到布线轨道，至少一些开关是连接开关可耦合到多个位线B中的一个，每个位线与列相关联。

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