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    • 2. 发明授权
    • Sensing circuit for a multi-level signal charge
    • 用于多电平信号电荷的感应电路
    • US4181865A
    • 1980-01-01
    • US900860
    • 1978-04-28
    • Susumu Kohyama
    • Susumu Kohyama
    • G11C11/56G11C19/28G11C19/36G11C27/04H03H11/26H03K3/353H03K5/08H03K5/20G11C7/06H03K3/286
    • G11C11/565G11C19/285G11C19/36G11C11/5642
    • This multi-level signal charge sensing circuit includes a first capacitor for holding inspected charge, a second capacitor for holding a plurality of reference charge levels and a comparator for comparing potentials produced at the first and second capacitors. As the plurality of reference charge levels, (N-1) charge levels of different known values are prepared. The inspected charge is given to the first capacitor which is reset, and the (N-1) reference charge levels are successively given from the highest or lowest level to the second capacitor which is also reset. The comparator is operated for every step of supplying each reference charge level. Of the successive reference charge supplying steps at an instant between the steps corresponding to 0 and (N-1), the output state of the comparator is inverted, thus supplying digital information representing the inspected charge level. This sensing circuit permits discrimination and sensing or detection of N different inspected charge levels with a single circuit construction.
    • 该多电平信号电荷感测电路包括用于保持检查电荷的第一电容器,用于保持多个参考电荷电平的第二电容器和用于比较在第一和第二电容器产生的电位的比较器。 作为多个参考电荷电平,准备不同已知值的(N-1)电荷电平。 对被复位的第一电容器进行检查的电荷,并且从最高或最低电平连续给出也被复位的第二电容器的(N-1)基准电荷电平。 比较器为每个参考电荷电平的每个步骤运行。 在对应于0和(N-1)的步骤之间的时刻的连续参考电荷提供步骤中,比较器的输出状态被反转,从而提供表示检查的充电电平的数字信息。 该感测电路允许使用单个电路结构来区分和检测N个不同的检查电荷水平。
    • 7. 发明授权
    • Multi-channel charge coupled transfer device
    • 多通道电荷耦合传输装置
    • US4211937A
    • 1980-07-08
    • US955212
    • 1978-10-27
    • Susumu Kohyama
    • Susumu Kohyama
    • G11C19/28H01L27/105H01L29/78H03K5/00
    • H01L27/1057G11C19/282G11C19/287
    • An electrode per bit (E/B) structure type charge transfer device in which N storage cell each consisting of a barrier region and a storage region are driven by N-phase clocks, one of N storage cells being empty and the remaining N-1 cells storing signal charge packets. The N-phase clocks are biased to a low level for storage and pulsed to a high level for transfer. The N storage cells are successively rendered in the transfer mode in the direction opposite to the charge transfer direction so that the empty cell is shifted to the adjacent preceding cell in the direction opposite to the charge transfer direction every time each of the N-phase clocks is pulsed. After one cycle of the N-phase clocks, all the signal charge packets are shifted to the succeeding cells respectively. A multiplexed electrode per bit (ME/B) structure type charge transfer device also is disclosed which employs the E/B structure and is operable by the clocks with small number of phases, providing a CCD memory with a large capacity.
    • 每个由位置(E / B)结构的电荷转移装置,其中由存储区域和存储区域组成的N个存储单元由N相时钟驱动,N个存储单元之一为空,而剩余的N-1 存储信号电荷包的单元。 N相时钟偏置为低电平存储,并且脉冲到高电平以进行传输。 N个存储单元在与电荷传输方向相反的方向上以传送模式连续呈现,使得每个N相时钟每次,空单元在与电荷传输方向相反的方向上移位到相邻的前一单元 是脉冲的。 在N相时钟的一个周期之后,所有的信号电荷分组分别移动到后续的信元。 公开了一种使用E / B结构的每位多路复用电极(ME / B)结构型电荷转移装置,可由具有少量相位的时钟操作,提供具有大容量的CCD存储器。