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1. 发明授权

US5384152A Method for forming capacitors with roughened single crystal plates 失效
标题翻译：用粗糙单晶板形成电容器的方法
公开(公告)号：US5384152A
公开(公告)日：1995-01-24
申请号：US69473
申请日：1993-06-01
申请人： Jack C. Chu , Louis Lu-Chen Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
发明人： Jack C. Chu , Louis Lu-Chen Hsu , Toshio Mii , Joseph F. Shepard , Scott R. Stiffler , Manu J. Tejwani , Edward J. Vishnesky
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L21/70 , B05D5/12
CPC分类号： H01L28/84 , H01L29/94 , Y10S438/964
摘要： A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.
摘要翻译：提供一种电容器，其具有衬底，并且包括晶格失配的晶体材料的第一电容器板形成在衬底的表面上并由衬底的表面支撑。一层绝缘材料形成在第一电容器板上并由其支撑。包括导电材料层的第二电容器板形成在绝缘材料层的上方并由其支撑。

2. 发明授权

US5622881A Packing density for flash memories 失效
标题翻译：闪存的包装密度
公开(公告)号：US5622881A
公开(公告)日：1997-04-22
申请号：US319393
申请日：1994-10-06
申请人： Joyce E. Acocella , Carol Galli , Louis Lu-Chen Hsu , Seiki Ogura , Nivo Rovedo , Joseph F. Shepard
发明人： Joyce E. Acocella , Carol Galli , Louis Lu-Chen Hsu , Seiki Ogura , Nivo Rovedo , Joseph F. Shepard
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546 , Y10S148/117 , Y10S438/981
摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.
摘要翻译：通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

3. 发明申请

US20120248567A1 LAYERED STRUCTURE WITH FUSE 有权
标题翻译：带保险丝的层状结构
公开(公告)号：US20120248567A1
公开(公告)日：2012-10-04
申请号：US13494327
申请日：2012-06-12
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.
摘要翻译：一个结构。该结构包括：衬底，衬底中的第一电极，衬底和第一电极上的第一电介质层，第一电介质层上方的第二电介质层和埋在第一电介质层中的熔丝元件。第一电极包括第一导电材料。第一电介质层的顶表面比第一电介质层的任何其它表面更远离第一电极的顶表面。第一电介质层包括第一电介质材料和第二电介质材料。第二电介质层的底表面与第一电介质层的顶表面直接物理接触。第二电介质层包括第二电介质材料。

4. 发明授权

US07984408B2 Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering 有权
标题翻译：结合了具有减小的结电容和漏极引起的屏障降低的半导体器件结构
公开(公告)号：US07984408B2
公开(公告)日：2011-07-19
申请号：US11875013
申请日：2007-10-19
申请人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack Allan Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack Allan Mandelman , Haining Yang
IPC分类号： G06F17/50 , H01L29/76
CPC分类号： H01L29/78603 , G11C29/54 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66772
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：用于设计，制造或测试设计的机器可读介质中体现的设计结构。该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。

5. 发明授权

US07968949B2 Contact forming method and related semiconductor device 有权
标题翻译：接触形成方法及相关半导体器件
公开(公告)号：US07968949B2
公开(公告)日：2011-06-28
申请号：US11668717
申请日：2007-01-30
申请人： Daniel C. Edelstein , Louis Lu-Chen Hsu , Chih-Chao Yang
发明人： Daniel C. Edelstein , Louis Lu-Chen Hsu , Chih-Chao Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76829 , H01L21/76831 , H01L29/6653 , H01L29/78
摘要： Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).
摘要翻译：公开了触点形成方法和相关的半导体器件。一种方法包括在结构和衬底上形成第一衬里，第一衬套覆盖结构的侧壁; 在所述第一衬垫和所述结构上形成介电层; 在所述介电层中形成与所述第一衬垫的接触孔; 在所述接触孔中形成第二衬垫，包括覆盖所述侧壁的所述第一衬套上方; 在接触孔的底部移除第一和第二衬垫; 并用导电材料填充接触孔以形成接触。结构侧壁上较厚的衬套防止短路，并允许至少保持一个或多个衬套中的任何固有应力。

6. 发明授权

US07833873B2 Method and structure to reduce contact resistance on thin silicon-on-insulator device 有权
公开(公告)号：US07833873B2
公开(公告)日：2010-11-16
申请号：US12174683
申请日：2008-07-17
申请人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
发明人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
IPC分类号： H01L21/76
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

7. 发明申请

US20100277210A1 THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION 有权
标题翻译：三维芯片堆叠同步
公开(公告)号：US20100277210A1
公开(公告)日：2010-11-04
申请号：US12432801
申请日：2009-04-30
申请人： Ping-Chuan Wang , Anthony R. Bonaccio , Jong-Ru Guo , Louis Lu-Chen Hsu
发明人： Ping-Chuan Wang , Anthony R. Bonaccio , Jong-Ru Guo , Louis Lu-Chen Hsu
IPC分类号： H03L7/06
CPC分类号： H03L7/099 , H03L7/18 , H03L7/22
摘要： a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.
摘要翻译：中心参考时钟被放置在3-D芯片堆叠的基本上中间的芯片中。中心参考时钟被分配给3-D芯片组的每个子芯片，从而以同步的方式为3-D堆叠中的每个芯片生成多个时钟。采用预定数量的通硅通孔和片上导线来形成每个从时钟的延迟元件，确保为每个子芯片生成的时钟基本上同步。可选地，嵌入式片上时钟微调电路用于进一步精确调谐以消除本地时钟偏移。

8. 发明申请

US20100261318A1 3D CHIP-STACK WITH FUSE-TYPE THROUGH SILICON VIA 有权
公开(公告)号：US20100261318A1
公开(公告)日：2010-10-14
申请号：US12822459
申请日：2010-06-24
申请人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
发明人： Kai Di Feng , Louis Lu-Chen Hsu , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/82
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5256 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/3011 , H01L2924/00014
摘要： Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

9. 发明授权

US07809340B2 Apparatus for implementing enhanced hand shake protocol in microelectronic communication systems 失效
标题翻译：用于在微电子通信系统中实现增强的手抖动协议的装置
公开(公告)号：US07809340B2
公开(公告)日：2010-10-05
申请号：US12127159
申请日：2008-05-27
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , James Stephen Mason
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , James Stephen Mason
IPC分类号： H04B1/04
CPC分类号： H04B1/38
摘要： An apparatus is provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common 10 mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the 15 transmitter terminates communications, drops the common mode level with the idle input being activated.
摘要翻译：提供了一种用于实现用于微电子通信系统的增强的手抖动协议的装置。发射机和接收机通过传输链路耦合在一起。发射机接收空闲输入。当发射机不发送数据并且发射机向接收单元施加第一公共10模式电平时，空闲输入被激活。当发射机准备好传输数据并且发射机将共模电平提升到接收单元时，空闲输入被去激活。响应于接收机检测共模水平上移，接收器接收发送的数据信号。在发送所需数据之后，15个发射机终止通信，在空闲输入被激活时降低共模电平。

10. 发明申请

US20090115448A1 Design Structure for an Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry 失效
标题翻译：自动驱动器/传输线/接收机阻抗匹配电路的设计结构
公开(公告)号：US20090115448A1
公开(公告)日：2009-05-07
申请号：US11934825
申请日：2007-11-05
申请人： Wagdi W. Abadeer , Louis Lu-Chen Hsu , Jack A. Mandelman
发明人： Wagdi W. Abadeer , Louis Lu-Chen Hsu , Jack A. Mandelman
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03J3/185 , H03L7/08 , H03L7/0805 , H03L7/0891
摘要： A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.
摘要翻译：用于阻抗匹配器的设计结构，其自动匹配驱动器和接收器之间的阻抗。阻抗匹配器的设计结构包括锁定到由驱动器提供的数据信号的锁相环（PLL）电路。阻抗匹配器还包括响应于PLL电路内的一个或多个压控振荡器控制信号的可调阻抗匹配电路，以产生与接收器阻抗匹配的输出信号。

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