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1. 发明授权

US07833873B2 Method and structure to reduce contact resistance on thin silicon-on-insulator device 有权
公开(公告)号：US07833873B2
公开(公告)日：2010-11-16
申请号：US12174683
申请日：2008-07-17
申请人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
发明人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
IPC分类号： H01L21/76
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

2. 发明申请

US20080274597A1 METHOD AND STRUCTURE TO REDUCE CONTACT RESISTANCE ON THIN SILICON-ON-INSULATOR DEVICE 有权
公开(公告)号：US20080274597A1
公开(公告)日：2008-11-06
申请号：US12174683
申请日：2008-07-17
申请人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
发明人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
IPC分类号： H01L21/336
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

3. 发明授权

US07687865B2 Method and structure to reduce contact resistance on thin silicon-on-insulator device 失效
标题翻译：减薄绝缘体上硅器件接触电阻的方法和结构
公开(公告)号：US07687865B2
公开(公告)日：2010-03-30
申请号：US12174673
申请日：2008-07-17
申请人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
发明人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
IPC分类号： H01L29/76
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.
摘要翻译：一种降低绝缘体上硅器件上的接触电阻的方法（和系统），包括控制器件源极 - 漏极区域中的硅化物深度。

4. 发明授权

US07479437B2 Method to reduce contact resistance on thin silicon-on-insulator device 失效
标题翻译：降低绝缘体上硅器件接触电阻的方法
公开(公告)号：US07479437B2
公开(公告)日：2009-01-20
申请号：US11413010
申请日：2006-04-28
申请人： Brian J Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
发明人： Brian J Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
IPC分类号： H01L21/336
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method of reducing contact resistance on a silicon-on-insulator includes exposing sidewalls and a portion of a top surface of a source/drain region of the device, forming a porous silicon layer within a surface of the source/drain region, implanting dopants in the source/drain region, and forming a silicide layer over the source/drain region. The porous silicon layer is formed by forming a layer of p+ doping on the exposed sidewalls and portion of the top surface of the source/drain region, forming a nitride liner over the device, including the source/drain region and the layer of p+ doping, forming a planarized resist over the nitride liner, recessing the planarized resist and etching the nitride liner to expose portions of the source/drain region, and forming the porous silicon layer on the exposed portions of the source drain region.
摘要翻译：降低绝缘体上硅的接触电阻的方法包括暴露该器件源极/漏极区的侧壁和一部分上表面，在源/漏区的表面内形成多孔硅层，注入掺杂剂在源极/漏极区域中，并且在源极/漏极区域上形成硅化物层。通过在暴露的源极/漏极区域的顶表面的侧壁和部分上形成p +掺杂层形成多孔硅层，在器件上形成氮化物衬垫，包括源/漏区和p +掺杂层在所述氮化物衬垫上形成平坦化的抗蚀剂，使所述平坦化抗蚀剂凹陷并蚀刻所述氮化物衬垫以暴露所述源/漏区的部分，以及在所述源漏区的所述暴露部分上形成所述多孔硅层。

5. 发明申请

US20080272412A1 METHOD AND STRUCTURE TO REDUCE CONTACT RESISTANCE ON THIN SILICON-ON-INSULATOR DEVICE 失效
标题翻译：减薄绝缘体绝缘体器件接触电阻的方法与结构
公开(公告)号：US20080272412A1
公开(公告)日：2008-11-06
申请号：US12174673
申请日：2008-07-17
申请人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
发明人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
IPC分类号： H01L29/78
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.
摘要翻译：一种降低绝缘体上硅器件上的接触电阻的方法（和系统），包括控制器件源极 - 漏极区域中的硅化物深度。

6. 发明申请

US20080220581A1 OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS 有权
标题翻译：用于形成金属门和完全硅化的栅极效应晶体管的光热退火方法
公开(公告)号：US20080220581A1
公开(公告)日：2008-09-11
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

7. 发明授权

US07410852B2 Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US07410852B2
公开(公告)日：2008-08-12
申请号：US11408522
申请日：2006-04-21
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/8234 , H01L21/42
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

8. 发明授权

US07449374B2 Methods of manufacturing semiconductor devices with rotated substrates 有权
标题翻译：制造具有旋转衬底的半导体器件的方法
公开(公告)号：US07449374B2
公开(公告)日：2008-11-11
申请号：US11710382
申请日：2007-02-23
申请人： Matthias Hierlemann , Chun-Yung Sung , Brian J. Greene , Manfred Eller
发明人： Matthias Hierlemann , Chun-Yung Sung , Brian J. Greene , Manfred Eller
IPC分类号： H01L21/84
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , H01L29/78
摘要： Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.
摘要翻译：集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向旋转5至40度的角度定向在基板上。诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

9. 发明授权

US08039331B2 Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US08039331B2
公开(公告)日：2011-10-18
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

10. 发明授权

US07205639B2 Semiconductor devices with rotated substrates and methods of manufacture thereof 有权
标题翻译：具有旋转基板的半导体器件及其制造方法
公开(公告)号：US07205639B2
公开(公告)日：2007-04-17
申请号：US11076080
申请日：2005-03-09
申请人： Matthias Hierlemann , Chun-Yung Sung , Brian J. Greene , Manfred Eller
发明人： Matthias Hierlemann , Chun-Yung Sung , Brian J. Greene , Manfred Eller
IPC分类号： H01L29/04 , H01L31/00
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , H01L29/78
摘要： Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.
摘要翻译：集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向在0至45度之间旋转的角度定向在基板上。诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

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