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1. 发明申请

US20190228289A1 TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK 审中-公开
公开(公告)号：US20190228289A1
公开(公告)日：2019-07-25
申请号：US16370570
申请日：2019-03-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08 , G06N3/063
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

2. 发明授权

US09818058B2 Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation 有权
公开(公告)号：US09818058B2
公开(公告)日：2017-11-14
申请号：US15154169
申请日：2016-05-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06E1/00 , G06E3/00 , G06F15/18 , G06G7/00 , G06N3/02 , G06N3/04 , G06N3/063 , G06N3/08
CPC分类号： G06N3/04 , G06N3/02 , G06N3/0454 , G06N3/049 , G06N3/063 , G06N3/08 , G06N3/088
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.

3. 发明申请

US20160260008A1 TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION 有权
标题翻译：具有隐含记忆寻址功能的时分多重神经元模块，用于实现通用的适应性基底
公开(公告)号：US20160260008A1
公开(公告)日：2016-09-08
申请号：US15154169
申请日：2016-05-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/04 , G06N3/02 , G06N3/0454 , G06N3/049 , G06N3/063 , G06N3/08 , G06N3/088
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
摘要翻译：本发明的实施例涉及一种具有隐式存储器寻址的时分复用神经突触模块，用于实现通用适配基板。一个实施例包括神经突触装置，其包括维持多个神经元的神经元属性的存储装置。该模块还包括多个位图，其维持不同延迟时段的输入触发事件和多路处理器。处理器包括维持多个突触权重的存储器阵列。处理器以时分多路复用方式整合传入的触发事件。基于神经元属性和维持的突触权重来集成入射射击事件。

4. 发明授权

US09887623B2 Efficient voltage conversion 有权
公开(公告)号：US09887623B2
公开(公告)日：2018-02-06
申请号：US15291092
申请日：2016-10-12
申请人： International Business Machines Corporation
发明人： Leland Chang , Robert K. Montoye , Jae-sun Seo , Albert M. Young
IPC分类号： H02M3/07 , H02M3/155 , G06F1/26
CPC分类号： H02M3/07 , G06F1/26 , H02M3/155
摘要： An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.

5. 发明申请

US20160292569A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 审中-公开
标题翻译：神经网络可重构和可定制的一般用途电路
公开(公告)号：US20160292569A1
公开(公告)日：2016-10-06
申请号：US15182485
申请日：2016-06-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/08 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

6. 发明申请

US20160172970A1 EFFICIENT VOLTAGE CONVERSION 有权
标题翻译：有效的电压转换
公开(公告)号：US20160172970A1
公开(公告)日：2016-06-16
申请号：US14566944
申请日：2014-12-11
申请人： International Business Machines Corporation
发明人： Leland Chang , Robert K. Montoye , Jae-sun Seo , Albert M. Young
IPC分类号： H02M3/155
CPC分类号： H02M3/07 , G06F1/26 , H02M3/155
摘要： An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.
摘要翻译：一种用于提供片上电压调节功率的装置包括开关电容器电压转换电路，其接收升高的功率需求信号并且当升高的功率需求信号不活动时以基速率运行，并且当升高的功率需求信号有效。开关电容器电压转换电路包括一个辅助的晶体管组，当升高的功率需求信号有效时，当升高的功率需求信号没有被激活并使能时，它们被禁用。该装置还可以包括下垂检测电路，其监测所监视的功率信号并且响应于所监视的功率信号降低到选定的电压电平以下而激活升高的功率需求信号。所监视的功率信号可以是由开关电容器电压转换电路的输入电源提供的电压输入。本文还公开了相应的方法。

7. 发明申请

US20160110640A1 TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK 审中-公开
标题翻译：具有隐含存储器寻址功能的时分多路神经网络模块实现神经网络
公开(公告)号：US20160110640A1
公开(公告)日：2016-04-21
申请号：US14963133
申请日：2015-12-08
申请人： International Business Machines Corporation
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
摘要翻译：本发明的实施例涉及具有用于实现神经网络的隐式存储器寻址的时分多路复用神经突触模块。一个实施例包括维持多个神经元的神经元属性并维持不同时间步长的输入触发事件。对于每个时间步骤，用于所述时间步长的输入触发事件以时分复用方式被集成。基于保持的神经元属性来集成接收点火事件。对于每个时间步长，维护的神经元属性基于用于所述时间步长的集成的输入触发事件并行更新。

8. 发明授权

US09239984B2 Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network 有权
标题翻译：具有隐式存储器寻址的时分复用神经轴突模块，用于实现神经网络
公开(公告)号：US09239984B2
公开(公告)日：2016-01-19
申请号：US13725476
申请日：2012-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
摘要翻译：本发明的实施例涉及具有用于实现神经网络的隐式存储器寻址的时分多路复用神经突触模块。一个实施例包括维持多个神经元的神经元属性并维持不同时间步长的输入触发事件。对于每个时间步骤，用于所述时间步长的输入触发事件以时分复用方式被集成。基于保持的神经元属性来集成接收点火事件。对于每个时间步长，维护的神经元属性基于用于所述时间步长的集成的输入触发事件并行更新。

9. 发明申请

US20140180987A1 TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK 有权
标题翻译：具有隐含存储器寻址功能的时分多路神经网络模块实现神经网络
公开(公告)号：US20140180987A1
公开(公告)日：2014-06-26
申请号：US13725476
申请日：2012-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/08
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
摘要翻译：本发明的实施例涉及具有用于实现神经网络的隐式存储器寻址的时分多路复用神经突触模块。一个实施例包括维持多个神经元的神经元属性并维持不同时间步长的输入触发事件。对于每个时间步骤，用于所述时间步长的输入触发事件以时分复用方式被集成。基于保持的神经元属性来集成接收点火事件。对于每个时间步长，维护的神经元属性基于用于所述时间步长的集成的输入触发事件并行更新。

10. 发明申请

US20140180984A1 TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION 有权
标题翻译：具有隐含记忆寻址功能的时分多重神经元模块，用于实现通用的适应性基底
公开(公告)号：US20140180984A1
公开(公告)日：2014-06-26
申请号：US13725463
申请日：2012-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/02
CPC分类号： G06N3/04 , G06N3/02 , G06N3/0454 , G06N3/049 , G06N3/063 , G06N3/08 , G06N3/088
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
摘要翻译：本发明的实施例涉及一种具有隐式存储器寻址的时分复用神经突触模块，用于实现通用适配基板。一个实施例包括神经突触装置，其包括维持多个神经元的神经元属性的存储装置。该模块还包括多个位图，其维持不同延迟时段的输入触发事件和多路处理器。处理器包括维持多个突触权重的存储器阵列。处理器以时分多路复用方式整合传入的触发事件。基于神经元属性和维持的突触权重来集成入射射击事件。

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