专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11687148B1 Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS 有权
公开(公告)号：US11687148B1
公开(公告)日：2023-06-27
申请号：US17729638
申请日：2022-04-26
申请人： International Business Machines Corporation
发明人： Robert K. Montoye , Kevin Tien , Yutaka Nakamura , Jeffrey Haskell Derby , Martin Cochet , Todd Edward Takken , Xin Zhang
IPC分类号： G06F1/00 , G06F1/3296 , G06F1/324
CPC分类号： G06F1/3296 , G06F1/324
摘要： A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

2. 发明授权

US11061675B2 Vector cross-compare count and sequence instructions 有权
公开(公告)号：US11061675B2
公开(公告)日：2021-07-13
申请号：US16663505
申请日：2019-10-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey H. Derby , Robert K. Montoye , Dheeraj Sreedhar
IPC分类号： G06F9/30
摘要： Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.

3. 发明授权

US10564964B2 Vector cross-compare count and sequence instructions 有权
公开(公告)号：US10564964B2
公开(公告)日：2020-02-18
申请号：US15244570
申请日：2016-08-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey H. Derby , Robert K. Montoye , Dheeraj Sreedhar
IPC分类号： G06F9/30
摘要： Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.

4. 发明授权

US09887623B2 Efficient voltage conversion 有权
公开(公告)号：US09887623B2
公开(公告)日：2018-02-06
申请号：US15291092
申请日：2016-10-12
申请人： International Business Machines Corporation
发明人： Leland Chang , Robert K. Montoye , Jae-sun Seo , Albert M. Young
IPC分类号： H02M3/07 , H02M3/155 , G06F1/26
CPC分类号： H02M3/07 , G06F1/26 , H02M3/155
摘要： An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.

5. 发明授权

US09496854B2 High-speed latch circuits by selective use of large gate pitch 有权
标题翻译：高速锁存电路通过选择性地使用大栅极间距
公开(公告)号：US09496854B2
公开(公告)日：2016-11-15
申请号：US14642838
申请日：2015-03-10
申请人： International Business Machines Corporation
发明人： Leland Chang , Robert K. Montoye
IPC分类号： G06F17/50 , H03K3/356
CPC分类号： G06F17/505 , G06F17/5068 , H03K3/037 , H03K3/356104
摘要： An apparatus includes a latch circuit comprising a first set of transistors that propagate an input signal of the latch circuit to an output signal of the latch circuit and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal of the latch circuit wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal of a latch to an output signal of a latch. The method also includes fabricating a chip comprising the plurality of latching circuits.
摘要翻译：一种装置包括：锁存电路，包括将锁存电路的输入信号传播到锁存电路的输出信号的第一组晶体管，以及不将锁存电路的输入信号传播到输出信号的第二组晶体管其中用于第一组晶体管的栅极间距基本上大于第二组晶体管的栅极间距。本文还公开了一种用于改善电路性能的方法，包括接收与设计文件相关联的多个锁存电路的电子表示，并且增加用于多个锁存电路中的所选晶体管的晶体管栅极间距，其中所选择的晶体管包括传播锁存器的输入信号到锁存器的输出信号。该方法还包括制造包括多个锁存电路的芯片。

6. 发明申请

US20160292569A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 审中-公开
标题翻译：神经网络可重构和可定制的一般用途电路
公开(公告)号：US20160292569A1
公开(公告)日：2016-10-06
申请号：US15182485
申请日：2016-06-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/08 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

7. 发明申请

US20160172970A1 EFFICIENT VOLTAGE CONVERSION 有权
标题翻译：有效的电压转换
公开(公告)号：US20160172970A1
公开(公告)日：2016-06-16
申请号：US14566944
申请日：2014-12-11
申请人： International Business Machines Corporation
发明人： Leland Chang , Robert K. Montoye , Jae-sun Seo , Albert M. Young
IPC分类号： H02M3/155
CPC分类号： H02M3/07 , G06F1/26 , H02M3/155
摘要： An apparatus for providing on-chip voltage-regulated power includes a switched capacitor voltage conversion circuit that receives an elevated power demand signal and operates at a base rate when the elevated power demand signal is not active and at an elevated rate when the elevated power demand signal is active. The switched capacitor voltage conversion circuit comprises an auxiliary set of transistors that are disabled, when the elevated power demand signal is not active and enabled, when the elevated power demand signal is active. The apparatus may also include a droop detection circuit that monitors a monitored power signal and activates the elevated power demand signal in response to the monitored power signal dropping below a selected voltage level. The monitored power signal may be a voltage input provided by an input power supply for the switched capacitor voltage conversion circuit. A corresponding method is also disclosed herein.
摘要翻译：一种用于提供片上电压调节功率的装置包括开关电容器电压转换电路，其接收升高的功率需求信号并且当升高的功率需求信号不活动时以基速率运行，并且当升高的功率需求信号有效。开关电容器电压转换电路包括一个辅助的晶体管组，当升高的功率需求信号有效时，当升高的功率需求信号没有被激活并使能时，它们被禁用。该装置还可以包括下垂检测电路，其监测所监视的功率信号并且响应于所监视的功率信号降低到选定的电压电平以下而激活升高的功率需求信号。所监视的功率信号可以是由开关电容器电压转换电路的输入电源提供的电压输入。本文还公开了相应的方法。

8. 发明申请

US20160110640A1 TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK 审中-公开
标题翻译：具有隐含存储器寻址功能的时分多路神经网络模块实现神经网络
公开(公告)号：US20160110640A1
公开(公告)日：2016-04-21
申请号：US14963133
申请日：2015-12-08
申请人： International Business Machines Corporation
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
摘要翻译：本发明的实施例涉及具有用于实现神经网络的隐式存储器寻址的时分多路复用神经突触模块。一个实施例包括维持多个神经元的神经元属性并维持不同时间步长的输入触发事件。对于每个时间步骤，用于所述时间步长的输入触发事件以时分复用方式被集成。基于保持的神经元属性来集成接收点火事件。对于每个时间步长，维护的神经元属性基于用于所述时间步长的集成的输入触发事件并行更新。

9. 发明授权

US09239984B2 Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network 有权
标题翻译：具有隐式存储器寻址的时分复用神经轴突模块，用于实现神经网络
公开(公告)号：US09239984B2
公开(公告)日：2016-01-19
申请号：US13725476
申请日：2012-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
摘要翻译：本发明的实施例涉及具有用于实现神经网络的隐式存储器寻址的时分多路复用神经突触模块。一个实施例包括维持多个神经元的神经元属性并维持不同时间步长的输入触发事件。对于每个时间步骤，用于所述时间步长的输入触发事件以时分复用方式被集成。基于保持的神经元属性来集成接收点火事件。对于每个时间步长，维护的神经元属性基于用于所述时间步长的集成的输入触发事件并行更新。

10. 发明申请

US20140180987A1 TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK 有权
标题翻译：具有隐含存储器寻址功能的时分多路神经网络模块实现神经网络
公开(公告)号：US20140180987A1
公开(公告)日：2014-06-26
申请号：US13725476
申请日：2012-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/08
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.
摘要翻译：本发明的实施例涉及具有用于实现神经网络的隐式存储器寻址的时分多路复用神经突触模块。一个实施例包括维持多个神经元的神经元属性并维持不同时间步长的输入触发事件。对于每个时间步骤，用于所述时间步长的输入触发事件以时分复用方式被集成。基于保持的神经元属性来集成接收点火事件。对于每个时间步长，维护的神经元属性基于用于所述时间步长的集成的输入触发事件并行更新。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式