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1. 发明授权

US11270192B2 Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices 有权
公开(公告)号：US11270192B2
公开(公告)日：2022-03-08
申请号：US15917414
申请日：2018-03-09
申请人： International Business Machines Corporation
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/06 , G06N3/063 , G11C11/54 , G11C13/00 , G06N3/04 , G06N3/08
摘要： One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

2. 发明授权

US11216595B2 Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology 有权
公开(公告)号：US11216595B2
公开(公告)日：2022-01-04
申请号：US16578319
申请日：2019-09-21
申请人： International Business Machines Corporation
发明人： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
IPC分类号： G06F21/72 , G06F21/75 , G11C16/00
摘要： A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

3. 发明授权

US10997321B2 Encryption engine with an undetectable/tamper proof private key in late node CMOS technology 有权
公开(公告)号：US10997321B2
公开(公告)日：2021-05-04
申请号：US16578321
申请日：2019-09-21
申请人： International Business Machines Corporation
发明人： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
IPC分类号： G06F21/72 , G06F21/75 , G11C16/00
摘要： A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

4. 发明授权

US10594019B2 Wireless communications package with integrated antenna array 有权
公开(公告)号：US10594019B2
公开(公告)日：2020-03-17
申请号：US15368600
申请日：2016-12-03
申请人： International Business Machines Corporation , Ericsson AB
发明人： Christian W. Baks , Daniel J. Friedman , Xiaoxiong Gu , Duixian Liu , Alberto Valdes Garcia , Joakim Hallin , Ola Ragnar Tageman
IPC分类号： H01Q1/24 , H01Q1/22 , H01Q9/04 , H01Q21/06 , H01Q1/38 , H01Q1/48 , H01Q1/52 , H01Q21/24
摘要： Antenna package structures are provided to implement wireless communications packages. For example, an antenna package includes multilayer package substrate, a planar antenna array, antenna feed lines, and resistive transmission lines. The planar antenna array includes an array of active antenna elements and dummy antenna elements surrounding the array of active antenna elements. Each active antenna element is coupled to a corresponding one of the antenna feed lines, and each dummy antenna element is coupled to a corresponding one of the resistive transmission lines. Each resistive transmission line extends through the multilayer package substrate and is terminated in a same metallization layer of the multilayer package substrate.

5. 发明授权

US10211779B2 Boosting varactor capacitance ratio 有权
公开(公告)号：US10211779B2
公开(公告)日：2019-02-19
申请号：US15151786
申请日：2016-05-11
申请人： International Business Machines Corporation
发明人： Mark A. Ferriss , Daniel J. Friedman , Bodhisatwa Sadhu , Alberto Valdes-Garcia
IPC分类号： H03B5/12 , H03B7/06 , H03J3/18 , H03J3/20 , H03J3/22 , H03J5/02 , H03L7/099
摘要： A voltage controlled oscillator comprises a negative resistance, a first inductor, a fixed capacitor, and a frequency control component. The frequency control component comprises at least one varactor and at least a second inductor connected in series with the at least one varactor. A magnitude of an inductance of the second inductor is selected such that the frequency control component has an effective capacitance range larger than a capacitance range of the at least one varactor.

6. 发明申请

US20180181774A1 ENCRYPTION ENGINE WITH AN UNDETECTABLE/TAMPER-PROOF PRIVATE KEY IN LATE NODE CMOS TECHNOLOGY 有权
公开(公告)号：US20180181774A1
公开(公告)日：2018-06-28
申请号：US15389078
申请日：2016-12-22
申请人： International Business Machines Corporation
发明人： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
IPC分类号： G06F21/72 , G06F21/75 , H01L27/112 , H01L23/00
摘要： A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

7. 发明申请

US20180159203A1 WIRELESS COMMUNICATIONS PACKAGE WITH INTEGRATED ANTENNA ARRAY 审中-公开
公开(公告)号：US20180159203A1
公开(公告)日：2018-06-07
申请号：US15368600
申请日：2016-12-03
申请人： International Business Machines Corporation , Ericsson AB
发明人： Christian W. Baks , Daniel J. Friedman , Xiaoxiong Gu , Duixian Liu , Alberto Valdes Garcia , Joakim Hallin , Ola Ragnar Tageman
IPC分类号： H01Q1/22 , H01Q1/48 , H01Q21/24 , H01Q9/04 , H01Q1/52
CPC分类号： H01Q1/2283 , H01Q1/38 , H01Q1/48 , H01Q1/526 , H01Q9/0407 , H01Q9/045 , H01Q21/065 , H01Q21/24
摘要： Antenna package structures are provided to implement wireless communications packages. For example, an antenna package includes multilayer package substrate, a planar antenna array, antenna feed lines, and resistive transmission lines. The planar antenna array includes an array of active antenna elements and dummy antenna elements surrounding the array of active antenna elements. Each active antenna element is coupled to a corresponding one of the antenna feed lines, and each dummy antenna element is coupled to a corresponding one of the resistive transmission lines. Each resistive transmission line extends through the multilayer package substrate and is terminated in a same metallization layer of the multilayer package substrate.

8. 发明授权

US09460383B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
标题翻译：可重构和可定制的神经网络通用电路
公开(公告)号：US09460383B2
公开(公告)日：2016-10-04
申请号：US14475409
申请日：2014-09-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

9. 发明申请

US20160224890A1 PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES 有权
标题翻译：在使用相位变化的同步设备的神经网络中生产依赖于时间的相对塑性
公开(公告)号：US20160224890A1
公开(公告)日：2016-08-04
申请号：US14990721
申请日：2016-01-07
申请人： International Business Machines Corporation
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/08 , G06N3/04
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
摘要翻译：本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

10. 发明授权

US09373073B2 Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation 有权
标题翻译：具有隐式存储器寻址的时分复用神经突触模块，用于实现通用适应底物
公开(公告)号：US09373073B2
公开(公告)日：2016-06-21
申请号：US13725463
申请日：2012-12-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John V. Arthur , Bernard V. Brezzo , Leland Chang , Daniel J. Friedman , Paul A. Merolla , Dharmendra S. Modha , Robert K. Montoye , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06E1/00 , G06E3/00 , G06F15/18 , G06G7/00 , G06N3/02 , G06N3/063 , G06N3/04
CPC分类号： G06N3/04 , G06N3/02 , G06N3/0454 , G06N3/049 , G06N3/063 , G06N3/08 , G06N3/088
摘要： Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
摘要翻译：本发明的实施例涉及一种具有隐式存储器寻址的时分复用神经突触模块，用于实现通用适配基板。一个实施例包括神经突触装置，其包括维持多个神经元的神经元属性的存储装置。该模块还包括多个位图，其维持不同延迟时段的输入触发事件和多路处理器。处理器包括维持多个突触权重的存储器阵列。处理器以时分多路复用方式整合传入的触发事件。基于神经元属性和维持的突触权重来集成入射射击事件。

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