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1. 发明申请

US20040239390A1 Structure and method for dynamic control of output driver voltage 失效
标题翻译：输出驱动电压动态控制的结构和方法
公开(公告)号：US20040239390A1
公开(公告)日：2004-12-02
申请号：US10448762
申请日：2003-05-30
发明人： Jason Harold Culler
IPC分类号： H03K019/0175
CPC分类号： H03K4/023
摘要： A method and structure for control of a rise time of a bus signal coupled to a driver circuit. A bus is coupled to the driver circuit and is operable to carry the bus signal. Voltage control elements are coupled to the driver circuit and the bus, and are operable to increase or decrease a voltage of the bus signal relative to a ground at one or more time instants. A control circuit coupled to the voltage control elements is operable to control the switching of the voltage control elements, thereby controlling the voltage level of the bus signal. Controlling a rise time of the bus signal of the driver circuit includes adaptively adjusting a voltage level of the bus signal relative to a ground at one or more discrete times by the use of the voltage control elements.
摘要翻译：用于控制耦合到驱动器电路的总线信号的上升时间的方法和结构。总线耦合到驱动器电路并且可操作以承载总线信号。电压控制元件耦合到驱动器电路和总线，并且可操作以在一个或多个时刻增加或减少总线信号相对于地的电压。耦合到电压控制元件的控制电路可操作以控制电压控制元件的切换，从而控制总线信号的电压电平。控制驱动器电路的总线信号的上升时间包括通过使用电压控制元件在一个或多个离散时间自适应地调整总线信号相对于地的电压电平。

2. 发明申请

US20040227542A1 Digital logic with reduced leakage 有权
标题翻译：数字逻辑减少泄漏
公开(公告)号：US20040227542A1
公开(公告)日：2004-11-18
申请号：US10437764
申请日：2003-05-14
发明人： Azeez J. Bhavnagarwala , Suhwan Kim , Daniel R. Knebel , Stephen V. Kosonocky
IPC分类号： H03K019/0175
CPC分类号： H03K19/0016
摘要： A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.
摘要翻译：提供了功率门结构和相应的方法，用于控制用于多个模式的逻辑电路的接地连接，其中功率栅极结构包括NFET晶体管，与NFET晶体管信号通信的PFET晶体管，源极和漏极分别与晶体管的漏极信号通信的接地节点和与晶体管的源极信号通信的接地轨道; 并且相应的方法包括在第一或活动模式下将逻辑电路与接地连接解耦，在第二或状态保持模式下将逻辑电路保持在接地连接以上的阈值电压处，并且切断逻辑电流之间的电流电路和接地连接处于第三或非状态保持模式。

3. 发明申请

US20040217776A1 Semiconductor integrated circuit including first and second switching transistors having operation states corresponding to operation states of first and second logic circuits 有权
标题翻译：包括具有对应于第一和第二逻辑电路的操作状态的操作状态的第一和第二开关晶体管的半导体集成电路
公开(公告)号：US20040217776A1
公开(公告)日：2004-11-04
申请号：US10859141
申请日：2004-06-03
发明人： Masashi Horiguchi , Yasushi Kawase , Takesada Akiba , Yoshinobu Nakagome , Kazuhiko Kajigaya
IPC分类号： H03K019/0175
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.
摘要翻译：提供半导体集成电路，其具有分别耦合到第一和第二子电源线的第一和第二逻辑电路。还提供第一和第二开关晶体管以将第一和第二子电源线连接到主电源线。第一和第二开关晶体管被保持在第一和第二逻辑电路的操作停止状态，并且保持在第一和第二逻辑电路的可操作状态。

4. 发明申请

US20040174188A1 Information handling system featuring a BJT-based bi-directional level translator 有权
标题翻译：信息处理系统采用基于BJT的双向电平转换器
公开(公告)号：US20040174188A1
公开(公告)日：2004-09-09
申请号：US10379237
申请日：2003-03-04
申请人： Dell Products L.P.
发明人： Joseph D. Mallory , Nikolai V. Vyssotski
IPC分类号： H03K019/0175
CPC分类号： H03K19/01843
摘要： A method of implementing bi-directional level translation in an information handling system includes coupling a first device port via a first resistor to a first voltage. A second device port is coupled via a second resistor to a second voltage different from the first voltage. Lastly, a single bipolar junction transistor (BJT) couples the first device port to the second device port, the single bipolar junction transistor including an emitter coupled to the first device port, a base coupled via a third resistor to the first voltage, and a collector coupled to the second device port, wherein the bipolar junction transistor operates as a bi-directional level translator between the first and second device ports.
摘要翻译：在信息处理系统中实现双向电平转换的方法包括将第一设备端口经由第一电阻器耦合到第一电压。第二设备端口经由第二电阻器耦合到不同于第一电压的第二电压。最后，单个双极结晶体管（BJT）将第一器件端口耦合到第二器件端口，单个双极结晶体管包括耦合到第一器件端口的发射极，经由第三电阻器耦合到第一电压的基极，以及集电极耦合到第二器件端口，其中双极结晶体管在第一和第二器件端口之间作为双向电平转换器工作。

5. 发明申请

US20040169542A1 Level shift circuit 失效
标题翻译：电平移位电路
公开(公告)号：US20040169542A1
公开(公告)日：2004-09-02
申请号：US10792087
申请日：2004-03-04
发明人： Shinichi Kouzuma
IPC分类号： H03K019/0175
CPC分类号： H03K3/356113 , H03K3/012 , H03K17/164
摘要： A level shift circuit whereby a voltage shift amount is large, operation speed is fast, and the power consumption is low. A p-type first transistor is connected between the power supply line and the first node, a p-type second transistor is connected between the power supply line and the second node, and an n-type third transistor is connected between the ground line and the first node, and an n-type fourth transistor is connected between the ground line and the second node. The gate of the first transistor is connected to the second node, and the gate of the second transistor is connected to the first node. An input signal is supplied to the gate of the third transistor and an inverted value of the input signal is supplied to the gate of the fourth transistor. Additionally, this level shift circuit has a plurality of control transistors. The control transistor switches the ratio of the inflow current and emission current of the first node or the second node according to the control signal. The operation speed increases if this ratio is set high, and the voltage shift amount increases if this ratio is set low.
摘要翻译：电压移位电路，电压偏移量大，操作速度快，功耗低。 p型第一晶体管连接在电源线和第一节点之间，p型第二晶体管连接在电源线和第二节点之间，n型第三晶体管连接在地线和第一节点和n型第四晶体管连接在地线和第二节点之间。第一晶体管的栅极连接到第二节点，第二晶体管的栅极连接到第一节点。输入信号被提供给第三晶体管的栅极，并且输入信号的反相值被提供给第四晶体管的栅极。此外，该电平移位电路具有多个控制晶体管。控制晶体管根据控制信号切换第一节点或第二节点的流入电流和发射电流的比例。如果该比率设置为高，则运行速度增加，并且如果该比率被设置为低，则电压偏移量增加。

6. 发明申请

US20040150425A1 Output signal circuit capable of automatically detecting polarity 失效
标题翻译：输出信号电路能够自动检测极性
公开(公告)号：US20040150425A1
公开(公告)日：2004-08-05
申请号：US10358169
申请日：2003-02-05
发明人： Bar-Chung Hwang , Jin-Chyuan Fuh
IPC分类号： H03K019/0175
CPC分类号： G01R19/14
摘要： The present invention proposes an output signal circuit capable of automatically detecting polarity, whose input/output signal terminal of the output signal circuit has both input and output functions. When a system undergoes a power on reset or a hardware reset, the output signal circuit can be shut off, and the input state of the input/output signal terminal is used to set the polarity of output signal. After reset, the pin is restored to its normal output. When an IC has the output signal capable of automatically detecting polarity, the flexibility in design of application circuits can be enhanced. Limitation of usage of IC due to fixed polarity of output signal can thus be avoided.
摘要翻译：本发明提出一种能够自动检测极性的输出信号电路，其输出信号电路的输入/输出信号端具有输入和输出功能。当系统经过电源复位或硬件复位时，可以关闭输出信号电路，并且使用输入/输出信号端子的输入状态来设置输出信号的极性。复位后，引脚恢复正常输出。当IC具有能够自动检测极性的输出信号时，可以提高应用电路设计的灵活性。因此可以避免由于输出信号的固定极性导致的IC的使用限制。

7. 发明申请

US20040119498A1 Converter from ECL to CMOS and network element for transmitting signals 有权
标题翻译：转换器从ECL到CMOS和传输信号的网元
公开(公告)号：US20040119498A1
公开(公告)日：2004-06-24
申请号：US10716475
申请日：2003-11-20
申请人： ALCATEL
发明人： Frank Ilchmann
IPC分类号： H03K019/0175
CPC分类号： H03K19/017527
摘要： The invention relates to a converter from ECL to CMOS having an input stage (Q1, Q2, N3, N4), a level shifter stage (N1, N2, N5, R1, R2, R3) including an NFET differential stage (N1, N2), and an output stage (P1, P2, P3, P4, N6, N7, N8, N9), and to a network element for transmitting signals which comprises a converter from ECL to CMOS having an input stage (Q1, Q2, N3, N4), a level shifter stage (N1, N2, N5, R1, R2, R3), and an output stage (P1, P2, P3, P4, N6, N7, N8, N9), with the level shifter stage (N1, N2, N5, R1, R2, R3) including an NFET differential stage (N1, N2).
摘要翻译：本发明涉及一种从ECL到CMOS的转换器，具有输入级（Q1，Q2，N3，N4），包括NFET差分级（N1，N2）的电平转换级（N1，N2，N5，R1，R2，R3））和输出级（P1，P2，P3，P4，N6，N7，N8，N9），以及用于发送信号的网络元件，其包括从ECL到具有输入级（Q1，Q2，N3 ，N4），电平移位器级（N1，N2，N5，R1，R2，R3）和输出级（P1，P2，P3，P4，N6，N7，N8，N9） N1，N2，N5，R1，R2，R3），包括NFET差分级（N1，N2）。

8. 发明申请

US20040100303A1 Three terminal noninverting transistor switch background of the invention 有权
标题翻译：本发明的三端子反相晶体管开关背景
公开(公告)号：US20040100303A1
公开(公告)日：2004-05-27
申请号：US10466789
申请日：2004-01-07
发明人： James S. Congdon
IPC分类号： H03K019/0175
CPC分类号： H03K17/04123 , H03K17/687 , H03K2217/0036
摘要： A noninverting transistor switch having only a first terminal, a second terminal and third terminal includes a transistor connected to the second and third terminals, the transistor having an on switching state in which current is able to pass between the second and third terminals and an off switching state in which current is interrupted from passing between the second and third terminals. The transistor switch also includes a voltage stabilizer connected to the second and third terminals. The transistor switch further includes a CMOS inverter connected to the first terminal, the second terminal, the transistor and the voltage stabilizer. In use, the CMOS inverter interrupts the passing of current between the voltage stabilizer and the second terminal when the transistor is in its off switching state.
摘要翻译：仅具有第一端子，第二端子和第三端子的同相晶体管开关包括连接到第二和第三端子的晶体管，晶体管具有导通开关状态，其中电流能够在第二和第三端子之间通过，并且断开开关状态，其中电流被中断从第二和第三端子之间通过。晶体管开关还包括连接到第二和第三端子的稳压器。晶体管开关还包括连接到第一端子，第二端子，晶体管和稳压器的CMOS反相器。在使用中，当晶体管处于截止状态时，CMOS反相器中断电压稳定器与第二端子之间的电流通过。

9. 发明申请

US20040090243A1 Output buffer circuits including logic gates having balanced output nodes 有权
标题翻译：输出缓冲电路包括具有平衡输出节点的逻辑门
公开(公告)号：US20040090243A1
公开(公告)日：2004-05-13
申请号：US10701321
申请日：2003-11-04
发明人： Joung-Yeal Kim
IPC分类号： H03K019/0175
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A buffer circuit may include an output terminal, a pull-up transistor, a pull-down transistor, and first and second logic gates. The pull-up transistor is connected between the output terminal and a supply voltage, and the pull-up transistor pulls the output terminal up to the supply voltage responsive to a pull-up control signal. The pull-down transistor is connected between the output terminal and a reference voltage, and the pull-down transistor pulls the output terminal down to the reference voltage responsive to a pull-down control signal. The first logic gate may generate the pull-up control signal at a first output node responsive to a control signal and a data signal, and the first logic gate may include a plurality of serially connected transistors in an electrical path between the supply voltage and the first output node. The second logic gate may generate the pull-down control signal at a second output node responsive to the data signal and an inverse of the control signal, and the second logic gate may include a plurality of serially connected transistors in a path between the supply voltage and the second output node.
摘要翻译：缓冲电路可以包括输出端子，上拉晶体管，下拉晶体管以及第一和第二逻辑门。上拉晶体管连接在输出端子和电源电压之间，并且上拉晶体管响应于上拉控制信号将输出端子拉至电源电压。下拉晶体管连接在输出端子和参考电压之间，并且下拉晶体管响应于下拉控制信号将输出端子下拉到参考电压。第一逻辑门可以响应于控制信号和数据信号而在第一输出节点产生上拉控制信号，并且第一逻辑门可以包括电源电压和电源电压之间的电气路径中的多个串联连接的晶体管第一个输出节点。第二逻辑门可以响应于数据信号和控制信号的反相而在第二输出节点处产生下拉控制信号，并且第二逻辑门可以包括在电源电压之间的路径中的多个串联连接的晶体管和第二输出节点。

10. 发明申请

US20040085094A1 Dividing and distributing the drive strength of a single clock buffer 有权
标题翻译：分配和分配单个时钟缓冲区的驱动强度
公开(公告)号：US20040085094A1
公开(公告)日：2004-05-06
申请号：US10288407
申请日：2002-11-04
申请人： Sun Microsystems, Inc.
发明人： David Hogenmiller , Harsh Sharma , Shervin Hojat
IPC分类号： H03K019/0175
CPC分类号： G06F1/04
摘要： Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer, to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.
摘要翻译：对时钟缓冲器的驱动强度进行分频和比例分配的装置，方法和网络，使得时钟缓冲器的输出驱动强度在来自时钟缓冲器的多个输出之间成比例地分配。在一个实施例中，本发明将存在于时钟缓冲器中的相邻并联逆变器选择性地耦合到分离的内部配线。内部配电线通过连接器线选择性地耦合到一个或多个输出，以提供从时钟缓冲器到时钟网络的驱动强度的成比例多输出。

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