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1. 发明授权

US06404579B1 Current bias voltage sense single ended preamplifier 有权
标题翻译：电流偏置电压检测单端前置放大器
公开(公告)号：US06404579B1
公开(公告)日：2002-06-11
申请号：US09699009
申请日：2000-10-27
申请人： Indumini Ranmuthu , Davy H Choi , Sami Kiriaki , Yong Han
发明人： Indumini Ranmuthu , Davy H Choi , Sami Kiriaki , Yong Han
IPC分类号： G11B503
CPC分类号： G11B5/02 , G11B5/012 , G11B2005/0016 , G11B2005/0018 , H03F1/56
摘要： Preamplifiers are used in hard disk drive applications to read data stored on magnetic disk. Current bias current sense preamplifiers have a problem with bandwidth rolloff due to relatively high inductance. Voltage sense preamplifiers have a problem with peaking due to input capacitance. An improved current bias voltage sense preamplifier inserts a PMOS transistor M3 between the Rmr head and the bipolar transistor Q0. The PMOS transistor M3 and the bipolar transistor Q0 form a high impedance voltage sense preamplifier. Biasing of the MR head is performed transistors M6 and M7 that mirror the current supplied by the current digital to analog converter into the MR head. Hence, the preamplifier is also of the current bias type. Peaking is controlled through a programmable current in an input capacitance cancellation circuit 30.
摘要翻译：前置放大器用于硬盘驱动器应用程序以读取存储在磁盘上的数据。电流偏置电流检测前置放大器由于相对较高的电感而带宽滚降的问题。电压感应前置放大器由于输入电容而导致峰值问题。改进的电流偏置电压感测前置放大器在Rmr头和双极晶体管Q0之间插入PMOS晶体管M3。 PMOS晶体管M3和双极晶体管Q0形成高阻抗电压感测前置放大器。执行MR磁头的偏置，将由当前数模转换器提供的电流镜像到MR磁头中的晶体管M6和M7。因此，前置放大器也是电流偏置型。峰值通过输入电容消除电路30中的可编程电流来控制。

2. 发明申请

US20120300606A1 Current Driver Damping Circuit 有权
标题翻译：电流驱动器阻尼电路
公开(公告)号：US20120300606A1
公开(公告)日：2012-11-29
申请号：US13118242
申请日：2011-05-27
申请人： Shengyuan Li , Douglas Warren Dean , Indumini Ranmuthu
发明人： Shengyuan Li , Douglas Warren Dean , Indumini Ranmuthu
IPC分类号： G11B7/13 , H02H9/00 , G05F3/02
CPC分类号： H01S5/042
摘要： Various apparatuses, methods and systems for damping a current driver are disclosed herein. For example, some embodiments provide an apparatus for supplying current, including an output transistor connected between a voltage supply and a current output, and an active clamp connected between the current output and a current sink. The active clamp is adapted to connect the current output to the current sink when a voltage at the current output reaches a predetermined state relative to a voltage at a control input of the output transistor.
摘要翻译：本文公开了用于阻尼电流驱动器的各种装置，方法和系统。例如，一些实施例提供一种用于提供电流的装置，包括连接在电压源和电流输出端之间的输出晶体管和连接在电流输出端与电流源之间的有源钳位。当电流输出端的电压相对于输出晶体管的控制输入处的电压达到预定状态时，有源钳位电路适于将电流输出连接到电流吸收器。

3. 发明申请

US20100166031A1 LASER DIODE DRIVER ARCHITECTURES 有权
标题翻译：激光二极管驱动器架构
公开(公告)号：US20100166031A1
公开(公告)日：2010-07-01
申请号：US12347311
申请日：2008-12-31
申请人： Shengyuan Li , Indumini Ranmuthu
发明人： Shengyuan Li , Indumini Ranmuthu
IPC分类号： H01S3/00
CPC分类号： H03K19/0175 , H01S5/0427
摘要： Laser diode driver architectures are disclosed. Some example current drivers are described, including a current channel to provide an output current. The current channel includes a current mirror with emitter degeneration, a startup transistor coupled to the current mirror to generate a DC bias on the current mirror, a beta helper circuit coupled to the current mirror and the startup transistor, to maintain the DC bias on the current mirror, and a cutoff transistor coupled to an emitter terminal of a current mirror transistor and to a reference voltage, to selectively couple the emitter terminal to the reference voltage to conduct the pre-determined output current. The example current drivers also include an output stage coupled to the output of the current mirror and to an output device, wherein the output stage provides a current gain in response to the cutoff transistor coupling the emitter terminal to the reference voltage.
摘要翻译：公开了激光二极管驱动器架构。描述了一些示例电流驱动器，包括提供输出电流的当前通道。电流通道包括具有发射极退化的电流镜，耦合到电流镜的启动晶体管，以在电流镜上产生DC偏置，耦合到电流镜和启动晶体管的β辅助电路，以将DC偏置保持在电流反射镜和耦合到电流镜晶体管的发射极端子和参考电压的截止晶体管，以将发射极端子选择性地耦合到参考电压以导通预定的输出电流。示例性电流驱动器还包括耦合到电流镜的输出和输出装置的输出级，其中响应于将发射极端子耦合到参考电压的截止晶体管，输出级提供电流增益。

4. 发明授权

US07152800B2 Preamplifier system having programmable resistance 有权
标题翻译：前置放大器系统具有可编程电阻
公开(公告)号：US07152800B2
公开(公告)日：2006-12-26
申请号：US10225956
申请日：2002-08-22
申请人： Indumini Ranmuthu , Yukihisa Hirotsugu , Mark Wolfe
发明人： Indumini Ranmuthu , Yukihisa Hirotsugu , Mark Wolfe
IPC分类号： G06K19/06
CPC分类号： G11B5/39 , G11B5/02
摘要： A biasing scheme is disclosed that helps reduce current noise in an associated device, such as, for example, a magneto-resistive device. The biasing scheme provides for setting a resistance path in a preamplifier, which is operative to energize the associated device, based on a biasing current that is to be used with associated device. Alternatively or additionally, the resistance path can be set based on a resistance of the associated device. As a result of setting the resistance path in this manner, noise through the associated device can be mitigated during its energization.
摘要翻译：公开了一种有助于降低相关设备（例如磁阻设备）中的电流噪声的偏置方案。偏置方案提供了在前置放大器中设置电阻路径，其基于要与相关联的装置一起使用的偏置电流来操作以对相关联的装置通电。或者或另外，可以基于相关联的装置的电阻来设置电阻路径。作为以这种方式设置电阻路径的结果，可以在其通电期间减轻通过相关联的装置的噪声。

5. 发明授权

US06473256B2 Method and apparatus for a 200 NS write to read switch time circuit 有权
标题翻译： 200 NS写入读取开关时间电路的方法和装置
公开(公告)号：US06473256B2
公开(公告)日：2002-10-29
申请号：US09212753
申请日：1998-12-16
申请人： Hae-Seok Cho , Indumini Ranmuthu
发明人： Hae-Seok Cho , Indumini Ranmuthu
IPC分类号： G11B1512
CPC分类号： G11B5/012 , G11B5/02 , G11B15/125 , G11B19/02 , G11B2005/0016
摘要： The present invention includes a circuit which can achieve a 200 nano second write to read time. The present invention eliminates a switch in the RMR measurement circuit.
摘要翻译：本发明包括可实现200纳秒写入读取时间的电路。本发明消除了RMR测量电路中的开关。

6. 发明授权

US08437232B2 High frequency modulator 有权
标题翻译：高频调制器
公开(公告)号：US08437232B2
公开(公告)日：2013-05-07
申请号：US12633072
申请日：2009-12-08
申请人： Akihiko Doi , Shengyuan Li , Indumini Ranmuthu
发明人： Akihiko Doi , Shengyuan Li , Indumini Ranmuthu
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B2007/0006
摘要： A high frequency modulator is described. It comprises: a first converter for receiving a constant current signal and transmitting a first converted signal; an adder coupled the first converter and operative for transmitting a summed signal in response to receiving the first converted signal and selectively receiving a triangular signal; a first oscillator coupled to the adder for receiving the summed signal, the first oscillator operative for transmitting a time varying current signal; a second converter coupled to the first oscillator for receiving the time varying current signal and operative for transmitting a second converted signal; and an output device selectively coupled to the second converter and operative for transmitting an output signal in response to receiving either the second converted signal or an offset signal.
摘要翻译：描述了高频调制器。它包括：第一转换器，用于接收恒定电流信号并发送第一转换信号; 耦合第一转换器的加法器，用于响应于接收到第一转换信号并选择性地接收三角形信号而发送加法信号; 第一振荡器，耦合到所述加法器，用于接收所述相加的信号，所述第一振荡器用于发送时变电流信号; 耦合到所述第一振荡器的第二转换器，用于接收所述时变电流信号并且用于发送第二转换信号; 以及选择性地耦合到第二转换器并且响应于接收到第二转换信号或偏移信号而发送输出信号的输出装置。

7. 发明申请

US20100315937A1 HIGH FREQUENCY MODULATOR 有权
标题翻译：高频调制器
公开(公告)号：US20100315937A1
公开(公告)日：2010-12-16
申请号：US12633072
申请日：2009-12-08
申请人： Akihiko Doi , Shengyuan Li , Indumini Ranmuthu
发明人： Akihiko Doi , Shengyuan Li , Indumini Ranmuthu
IPC分类号： G11B7/00 , H03C3/09 , G02F1/00
CPC分类号： G11B7/126 , G11B2007/0006
摘要： A high frequency modulator is described. It comprises: a first converter for receiving a constant current signal and transmitting a first converted signal; an adder coupled the first converter and operative for transmitting a summed signal in response to receiving the first converted signal and selectively receiving a triangular signal; a first oscillator coupled to the adder for receiving the summed signal, the first oscillator operative for transmitting a time varying current signal; a second converter coupled to the first oscillator for receiving the time varying current signal and operative for transmitting a second converted signal; and an output device selectively coupled to the second converter and operative for transmitting an output signal in response to receiving either the second converted signal or an offset signal.
摘要翻译：描述了高频调制器。它包括：第一转换器，用于接收恒定电流信号并发送第一转换信号; 耦合第一转换器的加法器，用于响应于接收到第一转换信号并选择性地接收三角形信号而发送加法信号; 第一振荡器，耦合到所述加法器，用于接收所述相加的信号，所述第一振荡器用于发送时变电流信号; 耦合到所述第一振荡器的第二转换器，用于接收所述时变电流信号并且用于发送第二转换信号; 以及选择性地耦合到第二转换器并且响应于接收到第二转换信号或偏移信号而发送输出信号的输出装置。

8. 发明申请

US20100246048A1 PREAMPLIFIER AND METHOD FOR SYNCHRONIZATION WITH BIT PATTERNED MEDIA 有权
标题翻译：用于与位图形媒体同步的前置放大器和方法
公开(公告)号：US20100246048A1
公开(公告)日：2010-09-30
申请号：US12576400
申请日：2009-10-09
申请人： Indumini Ranmuthu
发明人： Indumini Ranmuthu
IPC分类号： G11B5/02
CPC分类号： G11B5/09 , B82Y10/00 , G11B5/59616 , G11B5/59627 , G11B5/743 , G11B5/746 , G11B20/10194 , G11B20/10222 , G11B20/14 , G11B2220/2516
摘要： A preamplifier and method writes data synchronized with the passing of a write head in a magnetic storage device over bit islands in discrete patterned recording media. The preamplifier contains a write pre-driver that conditions write data, a synchronization circuit that accepts a delay offset value and a write clock and produces a delayed clock, and a write output driver that is gated by the delayed clock to produce write pulses for magnetizing the bit islands. Gating the write output driver using the delayed clock results in more accurate synchronization than delaying the write data into the preamplifier due to the reduction of the overall length and variability of interconnects and transistors in the intervening circuitry. Write clock generation circuitry, as well as bit position sensor circuitry for use with bit position signals produced by a read head or by a separate bit position sensor, are optionally integrated into the preamplifier, close to the write output driver and write head, for further improvements in delay accuracy and stability. Write pulses produced by the preamplifier are thus well aligned with the bit islands, resulting in higher magnetization and an improved bit error rate.
摘要翻译：前置放大器和方法将数据与写入磁头在磁存储设备中通过位离散图案记录介质上的位岛进行写入同步。前置放大器包含一个预写入数据的写入预驱动器，接收延迟偏移值和写入时钟并产生延迟时钟的同步电路，以及由延迟时钟门控产生用于磁化的写入脉冲的写入输出驱动器位岛。由于中间电路中互连和晶体管的总长度和可变性的减少，使用延迟时钟门控的写输出驱动器导致更准确的同步，从而将写入数据延迟到前置放大器。写入时钟生成电路以及用于由读取头或单独的位位置传感器产生的位位置信号的位位置传感器电路可选地集成到前置放大器中，靠近写入输出驱动器和写入头，用于进一步延迟精度和稳定性的改进。由前置放大器产生的写脉冲因此与位岛良好对准，导致更高的磁化强度和改进的误码率。

9. 发明申请

US20070127149A1 Offset cancellation scheme for perpendicular reader 审中-公开
标题翻译：垂直读取器的偏移取消方案
公开(公告)号：US20070127149A1
公开(公告)日：2007-06-07
申请号：US11292479
申请日：2005-12-02
申请人： Toru Takeuchi , Reza Sharifi , Indumini Ranmuthu
发明人： Toru Takeuchi , Reza Sharifi , Indumini Ranmuthu
IPC分类号： G11B5/02 , G11B5/09
CPC分类号： G11B5/02 , G11B2005/0013
摘要： A reader input amplifier for a hard disk drive including a gm-amp that compensates for any X-Y imbalance to reduce an excursion, and the time period of the excursion until a final settling point.
摘要翻译：一种用于硬盘驱动器的读取器输入放大器，包括补偿任何X-Y不平衡以减少偏移的gm放大器，以及偏移的时间段直到最终稳定点。

10. 发明授权

US07184232B2 Apparatus and method for driving a write head 有权
标题翻译：用于驱动写入头的装置和方法
公开(公告)号：US07184232B2
公开(公告)日：2007-02-27
申请号：US10665324
申请日：2003-09-18
申请人： Motomu Hashizume , Jinguji Naoko , Indumini Ranmuthu , Neel Seshan
发明人： Motomu Hashizume , Jinguji Naoko , Indumini Ranmuthu , Neel Seshan
IPC分类号： G11B5/09 , G11B5/02
CPC分类号： G11B5/09
摘要： An apparatus for driving a write head in response to a data signal includes: (a) a first drive unit coupled with the write head; (b) a second drive unit coupled with the write head; and (c) a control unit coupled with the first and second drive units. The control unit receives the data signal and generates control signals to the first drive and second drive units in response to the data signal. The control signals control the first drive unit to apply a first drive signal to a first write head side in a first signal polarity and control the second drive unit to apply a second drive signal to the a second write head side in a second signal polarity opposite to the first signal polarity when the data signal effects a signal excursion. The first drive signal and the second drive signal are equal in magnitude time coincident.
摘要翻译：一种用于响应于数据信号驱动写入头的装置包括：（a）与写入头耦合的第一驱动单元; （b）与写入头耦合的第二驱动单元; 和（c）与第一和第二驱动单元相连的控制单元。控制单元接收数据信号，并根据数据信号产生控制信号给第一驱动单元和第二驱动单元。控制信号控制第一驱动单元以第一信号极性将第一驱动信号施加到第一写头侧，并且控制第二驱动单元以与第二驱动单元相反的第二信号极性向第二写头侧施加第二驱动信号当数据信号影响信号偏移时，到第一个信号极性。第一驱动信号和第二驱动信号的幅度时间相等。

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