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1. 发明授权

US6035320A Fir filter architecture 失效
标题翻译：冷杉过滤器架构
公开(公告)号：US6035320A
公开(公告)日：2000-03-07
申请号：US368679
申请日：1995-01-04
申请人： Sami Kiriaki , William R. Krenik
发明人： Sami Kiriaki , William R. Krenik
IPC分类号： H03M1/66 , H03H17/06 , G06G7/02 , G06F17/10
CPC分类号： H03H17/06
摘要： A novel Finite Impulse Response filter (FIR) Filter is provided which includes a plurality of multipliers (14-22), a plurality of multiplexers (24-32), and a plurality of sample and hold circuits (34-42). At least two of the sample and hold circuit output signals (1-5) may be multiplexed in a round robin fashion to at least two of the multipliers (14-22). The multipliers may receive as a second input, fixed tap coefficient signals (C.sub.1 -C.sub.5) for multiplication with the multiplexed sample and hold circuit output signals (1-5).
摘要翻译：提供了一种新颖的有限脉冲响应滤波器（FIR）滤波器，其包括多个乘法器（14-22），多个复用器（24-32）和多个采样和保持电路（34-42）。至少两个采样和保持电路输出信号（1-5）可以以循环方式复用到至少两个乘法器（14-22）。乘法器可以接收作为第二输入的固定抽头系数信号（C1-C5），用于与复用的采样和保持电路输出信号（1-5）相乘。

2. 发明申请

US20050083108A1 Analog multiplexers with CMOS control signals 审中-公开
标题翻译：具有CMOS控制信号的模拟多路复用器
公开(公告)号：US20050083108A1
公开(公告)日：2005-04-21
申请号：US10983475
申请日：2004-11-08
申请人： Sami Kiriaki
发明人： Sami Kiriaki
IPC分类号： H03K17/16 , H03K17/693 , H03K19/177
CPC分类号： H03K17/162 , H03K17/693
摘要： Analog multiplexer circuits with CMOS control signals and with low signal feed-through and high bandwidth are described. These circuits emphasize low parasitic capacitance through circuit layout techniques and the use of smaller size n-channel transistors where possible. These circuits can be used for both single-ended and differential configurations. Two embodiments of the circuit are discussed allowing for optimal selection of multiplexers in application requirements ranging from lower-to-higher bandwidth and small-to-large input signal size.
摘要翻译：描述了具有CMOS控制信号和低信号馈通和高带宽的模拟多路复用器电路。这些电路通过电路布局技术强调低寄生电容，并尽可能地使用较小尺寸的n沟道晶体管。这些电路可用于单端和差分配置。讨论了电路的两个实施例，允许在从低到高带宽和小到大的输入信号尺寸范围内的应用需求中的多路复用器的最佳选择。

3. 发明授权

US06859814B2 Transpose FIR filter architecture 有权
标题翻译：转置FIR滤波器架构
公开(公告)号：US06859814B2
公开(公告)日：2005-02-22
申请号：US09851059
申请日：2001-05-08
申请人： Sami Kiriaki
发明人： Sami Kiriaki
IPC分类号： H03H15/00 , H03H17/06 , G06F17/10
CPC分类号： H03H15/00 , H03H17/06
摘要： A novel Finite Impulse Response (“FIR”) filter (100) is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (104). At least two slave sample and hold circuits (114, 118) connect to the master output. The slave sample and hold circuits (114, 118) operate at 1/k times the clock rate of the master sample and hold circuit (104), where k equals the number of slave sample and hold circuits (114, 118). A first multiplexer (126) multiplexes the slave outputs together. At least one tap block (129, 179, 207) is coupled to the first multiplexer (126) includes a multiplier (132, 180, 210), a summer (142, 142, 216), at least two slave sample and hold circuits (152, 154, 188, 190, 224, 226) and a second multiplexer (164, 200, 236). The slave sample and hold circuits (152, 154, 188, 190, 224, 226) run at 1/k times the clock speed of the master sample and hold circuit (126).
摘要翻译：提供了一种新颖的有限脉冲响应（“FIR”）滤波器（100）。采用主/从采样和保持架构。在该架构中，输入信号（VIN）耦合到主采样和保持电路（104）的输入端。至少两个从采样和保持电路（114,118）连接到主输出。从采样和保持电路（114,118）以主采样和保持电路（104）的时钟速率的1 / k倍工作，其中k等于从采样和保持电路（114,118）的数量。第一复用器（126）将从属输出复用在一起。至少一个抽头块（129,179,207）耦合到第一多路复用器（126），包括乘法器（132,180,210），加法器（142,142,216），至少两个从采样和保持电路（152,154,188,190,224,226）和第二多路复用器（164,200,236）。从采样和保持电路（152,154,188,190,224,226）以主采样和保持电路（126）的时钟速度的1 / k倍运行。

4. 发明授权

US06404579B1 Current bias voltage sense single ended preamplifier 有权
标题翻译：电流偏置电压检测单端前置放大器
公开(公告)号：US06404579B1
公开(公告)日：2002-06-11
申请号：US09699009
申请日：2000-10-27
申请人： Indumini Ranmuthu , Davy H Choi , Sami Kiriaki , Yong Han
发明人： Indumini Ranmuthu , Davy H Choi , Sami Kiriaki , Yong Han
IPC分类号： G11B503
CPC分类号： G11B5/02 , G11B5/012 , G11B2005/0016 , G11B2005/0018 , H03F1/56
摘要： Preamplifiers are used in hard disk drive applications to read data stored on magnetic disk. Current bias current sense preamplifiers have a problem with bandwidth rolloff due to relatively high inductance. Voltage sense preamplifiers have a problem with peaking due to input capacitance. An improved current bias voltage sense preamplifier inserts a PMOS transistor M3 between the Rmr head and the bipolar transistor Q0. The PMOS transistor M3 and the bipolar transistor Q0 form a high impedance voltage sense preamplifier. Biasing of the MR head is performed transistors M6 and M7 that mirror the current supplied by the current digital to analog converter into the MR head. Hence, the preamplifier is also of the current bias type. Peaking is controlled through a programmable current in an input capacitance cancellation circuit 30.
摘要翻译：前置放大器用于硬盘驱动器应用程序以读取存储在磁盘上的数据。电流偏置电流检测前置放大器由于相对较高的电感而带宽滚降的问题。电压感应前置放大器由于输入电容而导致峰值问题。改进的电流偏置电压感测前置放大器在Rmr头和双极晶体管Q0之间插入PMOS晶体管M3。 PMOS晶体管M3和双极晶体管Q0形成高阻抗电压感测前置放大器。执行MR磁头的偏置，将由当前数模转换器提供的电流镜像到MR磁头中的晶体管M6和M7。因此，前置放大器也是电流偏置型。峰值通过输入电容消除电路30中的可编程电流来控制。

5. 发明授权

US5838270A Second order and cascaded 2-1 oversampled modulators with improved dynamic range 失效
标题翻译：二级和级联2-1过采样调制器，具有改进的动态范围
公开(公告)号：US5838270A
公开(公告)日：1998-11-17
申请号：US371635
申请日：1995-01-12
申请人： Sami Kiriaki
发明人： Sami Kiriaki
IPC分类号： H03M1/08 , H03H17/02 , H03M3/02 , H03M3/00
CPC分类号： H03M3/448 , H03M3/418 , H03M3/43 , H03M3/454
摘要： An oversampled modulator (FIGS. 1 and 4) for operation in a frequency band from DC to a finyite frequency having a transfer function containing a plurality of zeros, at least two of which are disposed in the frequency band at a location other than at DC. The transfer function can have a plurality of zeros in the frequency band at a location other than at DC and at the same frequency. The second order version of the oversampled modulator has the transfer function: ##EQU1## where D(Z)=1+(A2-2)Z.sup.-1 +(1-A2+A1 S2+K S2)Z.sup.-2, X(Z)= input signal and Q(Z)=ADC quantization noise and the cascaded 2-1 embodiment has the transfer function: Y(Z)=Y.sub.1 (Z)(1+(b.sub.1 -1)(1-Z.sup.-1).sup.2)-Y.sub.2 (Z) (1/g.sub.2)(1-2Z.sup.-1 +(1+K)Z.sup.-2). The coefficient K is provided by a capacitor T-network. The value of K in the transfer functions can be programmable.
摘要翻译：用于在从DC到具有包含多个零的传递函数的频带的频带中操作的过采样调制器（图1和图4），其中至少两个调制器设置在除了DC之外的位置处的频带中。传递函数可以在除了在DC和相同频率之外的位置处的频带中具有多个零。过采样调制器的二阶版本具有传递函数：其中D（Z）= 1 +（A2-2）Z-1 +（1-A2 + A1 S2 + K S2）Z-2，X（Z ）=输入信号和Q（Z）= ADC量化噪声，级联2-1实施例具有传递函数：Y（Z）= Y1（Z）（1+（b1-1）（1-Z-1）2 ）-Y2（Z）（1 / g2）（1-2Z-1 +（1 + K）Z-2）。系数K由电容器T网络提供。传递函数中的K值可以编程。

6. 发明授权

US06369637B1 Analog BiCMOS multiplexers with CMOS control signals 有权
标题翻译：具有CMOS控制信号的模拟BiCMOS多路复用器
公开(公告)号：US06369637B1
公开(公告)日：2002-04-09
申请号：US09658777
申请日：2000-09-11
申请人： Sami Kiriaki
发明人： Sami Kiriaki
IPC分类号： H03K1762
CPC分类号： H03K17/6257
摘要： High-bandwidth, analog multiplexer circuits with low signal feed-through and good common mode properties are described. These are BiCMOS circuits with N-MOS control transistors which emphasize low parasitic capacitance through circuit layout techniques and the use of smaller geometry devices where possible. These circuits can be used in both single-ended and differential configurations and address applications having multiplexing ratio requirements ranging from 2-to-1 up to many-to-1.
摘要翻译：描述了具有低信号馈通和良好共模特性的高带宽模拟多路复用器电路。这些是具有N-MOS控制晶体管的BiCMOS电路，其通过电路布局技术强调低寄生电容，并且在可能的情况下使用较小的几何器件。这些电路可以用于单端和差分配置以及具有从2到1到多对1的复用比要求的地址应用。

7. 发明授权

US06337648B1 MOS transistor digital-to-analog converter 有权
标题翻译： MOS晶体管数模转换器
公开(公告)号：US06337648B1
公开(公告)日：2002-01-08
申请号：US09440015
申请日：1999-11-12
申请人： Sami Kiriaki
发明人： Sami Kiriaki
IPC分类号： H03M178
CPC分类号： H03M1/785
摘要： A monolithic, low power, digital-to-analog converter (DAC) circuit which uses an efficient transistor element to perform both switching and resistive current division functions simultaneously. This allows a R-2R type ladder network to be built using only conventional MOS transistors which can both switch and accurately divide current among the branches of the ladder network, without the need for separate resistors. The lower parts count and requirement for MOS transistors only, without the need for separate resistors, makes this circuit very compatible with low cost monolithic implementation. The DAC of this patent is useful in an application requiring the multiplication of two analog signals, where one of the signals is presented as a digital word. In this application, a Gilbert multiplier circuit is used to multiply the two signals, Vdig and Vsig, where Vdig represents the binary-weighted discrete levels from the DAC and Vsig is a continuous analog signal. Additionally, in order to obtain linear multiplication over a wide range, the Gilbert multiplier requires the use of a predistortion circuit in conjunction with the Vdig signal coming from the DAC to compensate for the logarithmic current-voltage transfer function of this circuit.
摘要翻译：一种单片，低功耗，数模转换器（DAC）电路，其使用有效的晶体管元件同时执行开关和电阻分流功能。这使得仅使用常规的MOS晶体管来构建R-2R型梯形网络，其可以在梯形网络的分支之间切换和精确地分配电流，而不需要单独的电阻器。仅对MOS晶体管的低部件数量和要求，而不需要单独的电阻器，使得该电路与低成本的单片实现非常兼容。该专利的DAC在需要两个模拟信号的乘法的应用中是有用的，其中一个信号被呈现为数字字。在本应用中，吉尔伯特乘法器电路用于乘以Vdig和Vsig两个信号，其中Vdig表示来自DAC的二进制加权离散电平，Vsig是连续的模拟信号。另外，为了在宽范围内获得线性乘法，吉尔伯特乘法器需要结合来自DAC的Vdig信号使用预失真电路来补偿该电路的对数电流 - 电压传递函数。

8. 发明授权

US6032171A Fir filter architecture with precise timing acquisition 失效
标题翻译：冷却过滤器架构，精确定时采集
公开(公告)号：US6032171A
公开(公告)日：2000-02-29
申请号：US368680
申请日：1995-01-04
申请人： Sami Kiriaki , Krishnasawamy Nagaraj , Kerry C. Glover
发明人： Sami Kiriaki , Krishnasawamy Nagaraj , Kerry C. Glover
IPC分类号： H03M1/08 , H03H17/06 , G06G7/02 , G06F17/10
CPC分类号： H03H15/00
摘要： A novel Finite Impulse Response ("FIR") filter (10)" is provided with precise timing acquisition. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (34). A plurality of slave sample and hold circuits (36-44) are coupled to the output of the master sample and hold circuit. The outputs of the slave sample and hold circuits (36-44) are multiplexed to a plurality of multipliers (14-22) in a round robin manner.
摘要翻译：提供了一种新颖的有限脉冲响应（“FIR”）滤波器（10）“精确定时采集。采用主/从采样和保持架构。在该结构中，输入信号（VIN）耦合到主采样和保持电路（34）的输入端。多个从采样和保持电路（36-44）耦合到主采样和保持电路的输出端。从采样保持电路（36-44）的输出以循环方式复用到多个乘法器（14-22）。

9. 发明授权

US5987038A Sync detect circuit 失效
标题翻译：同步检测电路
公开(公告)号：US5987038A
公开(公告)日：1999-11-16
申请号：US985038
申请日：1997-12-04
申请人： Bogdan Staszewski , Sami Kiriaki
发明人： Bogdan Staszewski , Sami Kiriaki
IPC分类号： H04L25/38 , G05B19/02 , G11B27/30 , H04L7/04 , H04L7/08
CPC分类号： G11B27/3027 , H04L7/042
摘要： A sync detect circuit is comprised of two serial data registers (40) and (42), each for storing a single word. A plurality of current sources in current source banks (44) and (46) are operable to convert the bits in the stored sync word to a differential current domain. Depending upon the logic state, the currents are added on two lines (50) and (52). When the differential current falls below a predetermined limit, a frame sync signal is generated to latch the next and following words into a data latch (34). These are then transferred out to a system upon the generation of a system data clock.
摘要翻译：同步检测电路由两个串行数据寄存器（40）和（42）组成，每个用于存储单个字。电流源极组（44）和（46）中的多个电流源可用于将所存储的同步字中的位转换为差分电流域。根据逻辑状态，电流被加到两条线（50）和（52）上。当差分电流下降到预定极限以下时，产生帧同步信号，以将下一个和后续字锁存到数据锁存器（34）中。然后在生成系统数据时钟时将这些数据传送到系统。

10. 发明授权

US5006853A Hysteresis insensitive analog to digital converter system using a coarse comparator and a fine comparator 失效
标题翻译：使用粗略比较器和精细比较器的滞后不敏感模数转换器系统
公开(公告)号：US5006853A
公开(公告)日：1991-04-09
申请号：US478596
申请日：1990-02-12
申请人： Sami Kiriaki , Khen-Sang Tan
发明人： Sami Kiriaki , Khen-Sang Tan
IPC分类号： H03M1/10 , H03M1/14 , H03M1/38 , H03M1/46 , H03M1/80
CPC分类号： H03M1/14 , H03M1/468 , H03M1/804
摘要： An analog to digital converter system (10) is disclosed which comprises an SAR logic circuit (12) which controls capacitor array control switches (14) which themselves control a capacitor array (16). A top plate (18) of the capacitor array (18) is selectively coupled to a coarse comparator (24) and a fine comparator (26). The outputs of the coarse comparator (24) and the fine comparator (26) are input into an error correction circuit (28). In operation, the coarse comparator (24) is used to approximate a predetermined number of the most significant bits of the digital word to be output by the system (10) while the fine comparator (26) is used to approximate the remaining bits of the digital word. In this manner, the coarse comparator (24) alone is subjected to the high voltages which might cause errors as a results of the hysteresis effect in the threshold voltages of the MOSFETs used to construct the comparators. The voltage shift as a result of this hysteresis is not a significant factor for the bits generated by the coarse comparator and as such the system (10) may accomplish high resolution analog to digital conversions.
摘要翻译：公开了一种模数转换器系统（10），其包括控制电容阵列控制开关（14）的SAR逻辑电路（12），其自身控制电容器阵列（16）。电容器阵列（18）的顶板（18）选择性地耦合到粗略比较器（24）和精细比较器（26）。粗略比较器（24）和精细比较器（26）的输出被输入到纠错电路（28）中。在操作中，粗略比较器（24）用于近似由系统（10）输出的数字字的预定数量的最高有效位，而精细比较器（26）用于近似该数字字的剩余位数字词以这种方式，粗略比较器（24）单独受到可能导致误差的高电压，作为用于构建比较器的MOSFET的阈值电压中的滞后效应的结果。作为这种滞后的结果的电压偏移不是由粗略比较器产生的位的重要因素，并且因此系统（10）可以实现高分辨率模数转换。

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