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    • 3. 发明授权
    • Graphics display list handler and method
    • 图形显示列表处理程序和方法
    • US06339427B1
    • 2002-01-15
    • US09211637
    • 1998-12-15
    • Indra LaksonoAntonio Asaro
    • Indra LaksonoAntonio Asaro
    • G06T1500
    • G06T15/005
    • A graphics display command list handler and method requests allocation of memory, such as system memory, in the form of a circular FIFO which stores the display command list as a memory display list (MDL), such as a host memory display list. A processor, such as a graphics processor, communicates a host memory display list read pointer to the host processor to facilitate display list signaling by the graphics processor. The host processor (or other processor) maintains a write pointer which points to a last host memory entry in the display list. The read pointer is maintained by the graphics processor and written back to the host processor.
    • 图形显示命令列表处理程序和方法请求以循环FIFO的形式分配诸如系统存储器的存储显示命令列表作为诸如主机存储器显示列表的存储器显示列表(MDL)的存储器。 诸如图形处理器的处理器将主机存储器显示列表读取指针传送到主机处理器以便于图形处理器的显示列表信令。 主机处理器(或其他处理器)维护写入指针,该指针指向显示列表中的最后一个主机存储器条目。 读指针由图形处理器维护并写回到主处理器。
    • 4. 发明授权
    • Method and apparatus for improved double buffering
    • 改进双缓冲的方法和装置
    • US6100906A
    • 2000-08-08
    • US64569
    • 1998-04-22
    • Antonio AsaroIndra LaksonoJames DoyleGordon F. Grigor
    • Antonio AsaroIndra LaksonoJames DoyleGordon F. Grigor
    • G09G5/36G09G5/39G09G5/393G09G5/399G06F13/00
    • G09G5/399G09G5/363
    • A method and apparatus for improved double buffering within a computing system begins when a series of data blocks are received from a central processing unit at a rate independent of a processing rate of a recipient engine. For example, a video graphics circuit receives a series of data blocks representing video frames from the central processing unit at a rate independent of the refresh rate of the display. As the data blocks are received, the video graphics circuit queues commands of the data blocks. Typically, the commands include processing commands and a processing rate synchronize command. To process the data blocks, the co-processor pulls commands from the queued list and processes them to produce recipient data. As the co-processor is producing the recipient data, it is utilizing a first buffer. The co-processor continues to process the commands and storing the results into the first buffer until the processing rate synchronize command is detected. At this point, the co-processor pauses processing of the commands. At the beginning of the next cycle of the processing rate, the recipient data is provided from the first buffer to the recipient engine and the co-processor resumes processing of commands, which relate to another data block. As the co-processor is processing the commands of the second data block, it is utilizing a second buffer to store the processed data, i.e., the second recipient data.
    • 一种用于在计算系统内改进双缓冲的方法和装置开始于以与接收机发动机的处理速率无关的速率从中央处理单元接收一系列数据块时开始。 例如,视频图形电路以与显示器的刷新率无关的速率从中央处理单元接收表示视频帧的一系列数据块。 当数据块被接收时,视频图形电路对数据块的命令进行排队。 通常,命令包括处理命令和处理速率同步命令。 为了处理数据块,协处理器从排队列表中提取命令并处理它们以产生接收方数据。 当协处理器产生接收者数据时,它正在利用第一缓冲器。 协处理器继续处理命令并将结果存储到第一缓冲器中,直到检测到处理速率同步命令。 此时,协处理器暂停处理命令。 在处理速率的下一周期的开始,从第一缓冲器向接收者引擎提供接收者数据,并且协处理器恢复与另一个数据块有关的命令的处理。 当协处理器正在处理第二数据块的命令时,它利用第二缓冲器来存储经处理的数据,即第二接收者数据。
    • 7. 发明授权
    • Apparatus and method for transmitting data
    • 用于传输数据的装置和方法
    • US06789154B1
    • 2004-09-07
    • US09579203
    • 2000-05-26
    • Brian LeeIndra LaksonoAntonio AsaroAndrew E. GruberGordon CarukMilivoje Aleksic
    • Brian LeeIndra LaksonoAntonio AsaroAndrew E. GruberGordon CarukMilivoje Aleksic
    • G06F1314
    • G06F13/404
    • In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
    • 在具体实施例中,公开了一种用于提供视频的系统,该系统具有系统总线,其在一个实施例中是高级图形端口(AGP)总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息,将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面,桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。
    • 9. 发明授权
    • Multiple device bridge apparatus and method thereof
    • 多设备桥接装置及其方法
    • US06662257B1
    • 2003-12-09
    • US09579202
    • 2000-05-26
    • Gordon CarukIndra LaksonoAntonio AsaroAndrew E. GruberMilivoje AleksicBrian Lee
    • Gordon CarukIndra LaksonoAntonio AsaroAndrew E. GruberMilivoje AleksicBrian Lee
    • G06F1314
    • G06F13/404G06F3/14
    • In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
    • 在具体实施例中,公开了一种用于提供视频的系统,该系统具有系统总线,其在一个实施例中是高级图形端口(AGP)总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息,将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面,桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。
    • 10. 发明授权
    • Method and apparatus for improved concurrent video graphic processing
    • 用于改进并发视频图形处理的方法和装置
    • US06195105B1
    • 2001-02-27
    • US09088190
    • 1998-06-01
    • Steven C. DilliplaneIndra LaksonoAntonio Asaro
    • Steven C. DilliplaneIndra LaksonoAntonio Asaro
    • G06T120
    • G06F9/3877G06F9/30025
    • A method and apparatus for improved concurrency within a video graphics process by generating culling information from geometry information. The geometry information corresponds to an image to be rendered, and the culling information indicates the triangles of the objects of the image that are in a front-facing or back-facing position. Having generated the culling information, set-up information is generated therefrom. The set-up information provides rendering data for the triangles of the object of the image being rendered. Next, pixel data is generated for a triangle based on the set-up information. To improve the concurrency, the queuing and the retrieval of the culling information and the set-up information from non-local memory are controlled such that the generating of the culling information, the set-up information, and the pixel data is done with improved concurrency.
    • 一种用于通过从几何信息生成剔除信息来改善视频图形过程中的并发性的方法和装置。 几何信息对应于要呈现的图像,并且剔除信息指示图像的处于前向或后向位置的图像的三角形。 生成了拣选信息后,从其生成设置信息。 设置信息提供正在呈现的图像的对象的三角形的渲染数据。 接下来,基于设置信息为三角形生成像素数据。 为了提高并发性,对来自非本地存储器的排队信息和设置信息的排队和检索进行控制,使得剔除信息,建立信息和像素数据的生成被改进 并发性