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1. 发明授权

US07543101B2 System of accessing data in a graphics system and method thereof 有权
标题翻译：在图形系统中访问数据的系统及其方法
公开(公告)号：US07543101B2
公开(公告)日：2009-06-02
申请号：US10075149
申请日：2002-02-14
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06F13/36
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

2. 发明授权

US06297832B1 Method and apparatus for memory access scheduling in a video graphics system 有权
标题翻译：视频图形系统中存储器访问调度的方法和装置
公开(公告)号：US06297832B1
公开(公告)日：2001-10-02
申请号：US09224692
申请日：1999-01-04
申请人： Carl K. Mizuyabu , Paul Chow , Philip L. Swan , Chun Wang
发明人： Carl K. Mizuyabu , Paul Chow , Philip L. Swan , Chun Wang
IPC分类号： G06G5399
CPC分类号： G06T1/60 , G06T15/005 , G09G5/39 , G09G2340/02 , G09G2360/12 , G09G2360/122 , G09G2360/123
摘要： A method and apparatus for sequencing memory accesses in a video graphics system such that page faults are effectively hidden is accomplished by receiving a memory access request from one of a plurality of clients, where the plurality of clients includes both linear clients and tiled memory clients. The clients access data stored in a memory that includes at least two banks. Once the memory request has been received, it is evaluated based on other pending requests in order to determine the optimal ordering pattern for execution of the memory requests. The optimal ordering pattern typically includes sequencing alternating accesses between the two banks of the memory such that when a page fault is occurring in one bank of the memory, a memory access is occurring in the opposing bank. Once the ordering of the memory requests has been performed, the requests are executed.
摘要翻译：一种用于对视频图形系统中的存储器访问进行排序的方法和装置，使得页面错误被有效地隐藏是通过从多个客户端之一接收存储器访问请求来实现的，其中多个客户端包括线性客户端和平铺存储器客户端。客户端访问存储在包含至少两个存储体的存储器中的数据。一旦接收到存储器请求，就基于其他挂起的请求来评估存储器请求，以便确定用于执行存储器请求的最佳排序模式。最优排序模式通常包括在存储器的两个存储体之间对交替访问进行排序，使得当在存储器的一个存储体中发生页面错误时，在相对的存储体中发生存储器访问。一旦执行了存储器请求的排序，就执行请求。

3. 发明授权

US06469703B1 System of accessing data in a graphics system and method thereof 有权
标题翻译：在图形系统中访问数据的系统及其方法
公开(公告)号：US06469703B1
公开(公告)日：2002-10-22
申请号：US09347202
申请日：1999-07-02
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06F15167
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，10个控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。

4. 发明授权

US06370630B1 Method and apparatus for controlling data flow in a data processor 有权
标题翻译：用于控制数据处理器中的数据流的方法和装置
公开(公告)号：US06370630B1
公开(公告)日：2002-04-09
申请号：US09272463
申请日：1999-03-19
申请人： Carl K. Mizuyabu , Andy E. Gruber , Brad Hollister
发明人： Carl K. Mizuyabu , Andy E. Gruber , Brad Hollister
IPC分类号： G06F1200
CPC分类号： G06F13/4243
摘要： A method and apparatus for accessing an external memory having a first width at at at a first data rate. The external data is reformatted to have a second predefined width larger than the first width. The data having the second predefined width is then provided at a second rate to one of several possible processing units.
摘要翻译：一种用于以第一数据速率访问具有第一宽度的外部存储器的方法和装置。将外部数据重新格式化为具有大于第一宽度的第二预定宽度。然后将具有第二预定义宽度的数据以第二速率提供给若干可能的处理单元之一。

5. 发明授权

US06326984B1 Method and apparatus for storing and displaying video image data in a video graphics system 有权
标题翻译：用于在视频图形系统中存储和显示视频图像数据的方法和装置
公开(公告)号：US06326984B1
公开(公告)日：2001-12-04
申请号：US09186034
申请日：1998-11-03
申请人： Paul Chow , Carl K. Mizuyabu , Philip L. Swan , Allen J.C. Porter , Chun Wang
发明人： Paul Chow , Carl K. Mizuyabu , Philip L. Swan , Allen J.C. Porter , Chun Wang
IPC分类号： G09G500
CPC分类号： G09G5/022 , G09G5/39 , G09G2340/02 , G09G2360/123 , H04N5/4401 , H04N5/44504 , H04N9/641 , H04N11/044 , H04N19/186 , H04N19/44 , H04N19/61 , H04N21/42653 , H04N21/4348 , H04N21/8146
摘要： A method and apparatus for storing and displaying video image data in a video graphics system is accomplished by receiving a video data stream, where the video data stream includes compressed video image data. The video image stream is parsed to separate the compressed video image data from other data within the data stream. The compressed video image data is decompressed to produce video image data that includes a luminosity plane, a first color plane, and a second color plane. Members of the first and second color planes are compacted together to form color pairs where a plurality of the color pairs form a color line. Each of the color lines is interleaved with at least one luminosity line to produce an interleaved plane. The interleaved plane is stored in memory. Portions of the interleaved video image data are retrieved from the interleaved plane. The portions are structured such that video image data that are located near each other within the memory are fetched together. A video output is generated based on the retrieved groups of image data where the luminosity and color values within each of the fetched groups of image data are utilized together to produce the video output.
摘要翻译：通过接收视频数据流来实现在视频图形系统中存储和显示视频图像数据的方法和装置，其中视频数据流包括压缩的视频图像数据。视频图像流被解析为将压缩的视频图像数据与数据流内的其他数据分离。压缩的视频图像数据被解压缩以产生包括亮度平面，第一颜色平面和第二颜色平面的视频图像数据。第一和第二颜色平面的成员被压缩在一起以形成多个颜色对形成彩色线的颜色对。每个颜色线与至少一个发光线交织以产生交错平面。交错平面存储在存储器中。从交织的平面检索交织的视频图像数据的一部分。这些部分被构造成使得在存储器内彼此靠近的视频图像数据被一起取出。基于检索到的图像数据组生成视频输出，其中每个获取的图像数据组中的亮度和颜色值一起被使用以产生视频输出。

6. 发明申请

US20090307406A1 Memory Device for Providing Data in a Graphics System and Method and Apparatus Thereof 有权
标题翻译：用于在图形系统中提供数据的存储器件及其方法和装置
公开(公告)号：US20090307406A1
公开(公告)日：2009-12-10
申请号：US12429833
申请日：2009-04-24
申请人： Milivoje Aleksic , Raymond M. Li , Danny H.M. Cheng , Carl K. Mizuyabu , Anthony Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H.M. Cheng , Carl K. Mizuyabu , Anthony Asaro
IPC分类号： G06F13/36
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

7. 发明授权

US06504549B1 Apparatus to arbitrate among clients requesting memory access in a video system and method thereof 有权
标题翻译：用于在视频系统中请求存储器访问的客户端进行仲裁的装置及其方法
公开(公告)号：US06504549B1
公开(公告)日：2003-01-07
申请号：US09314208
申请日：1999-05-19
申请人： Brad Holister , Andrew E. Gruber , Carl K. Mizuyabu
发明人： Brad Holister , Andrew E. Gruber , Carl K. Mizuyabu
IPC分类号： G06F1318
CPC分类号： G06F13/161 , G09G5/393 , G09G2360/12 , G09G2360/121
摘要： A method and apparatus dealing with optimizing the arbitration between clients requesting data. In particular, a set of rules determining which client request will provide an optimized subsequent memory access is implemented. The highest rule recognizes a client in urgent need of data, generally because it has not been services by the arbiter. The next highest-ranking rules would recognize data accesses of the same operation, such as read or write, and to the same page of memory, or requests to a different bank of memory. The next highest ranking rules would be for data accesses on the same page currently being accessed, but for a different operation, and for a different operation and to a different bank. Finally, any other client requests to a different page on the same bank/ would have the lowest priority. Such a request optimizes bandwidth of the memory bus.
摘要翻译：一种处理优化请求数据的客户端仲裁的方法和装置。特别地，实现了一组确定哪个客户端请求将提供优化的后续存储器访问的规则。最高规则意识到客户急需数据，通常是因为它没有由仲裁者提供服务。下一个最高级别的规则将识别相同操作的数据访问，例如读取或写入，以及同一页面的内存，或者请求到不同的存储器组。下一个最高排名的规则将是当前正在访问的同一页面上的数据访问，但是对于不同的操作，以及不同的操作和不同的银行。最后，任何其他客户端对同一个银行/其他页面的请求将具有最低优先级。这样的请求优化了存储器总线的带宽。

8. 发明授权

US08924617B2 Memory device for providing data in a graphics system and method and apparatus therof 有权
标题翻译：用于在图形系统中提供数据的存储器件以及方法和装置
公开(公告)号：US08924617B2
公开(公告)日：2014-12-30
申请号：US12429833
申请日：2009-04-24
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Anthony Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Anthony Asaro
IPC分类号： G06F13/14 , G09G5/39 , G06T1/60 , G09G5/393
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

9. 发明授权

US06546449B1 Video controller for accessing data in a system and method thereof 有权
标题翻译：用于访问系统中的数据的视频控制器及其方法
公开(公告)号：US06546449B1
公开(公告)日：2003-04-08
申请号：US09347201
申请日：1999-07-02
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06F1336
CPC分类号： G06F13/1684
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。

10. 发明授权

US06486884B1 Apparatus for accessing memory in a video system and method thereof 有权
标题翻译：一种用于在视频系统中访问存储器的装置及其方法
公开(公告)号：US06486884B1
公开(公告)日：2002-11-26
申请号：US09314561
申请日：1999-05-19
申请人： Milivoje Aleksic , Andrew E. Gruber , Brad Holister , Carl K. Mizuyabu
发明人： Milivoje Aleksic , Andrew E. Gruber , Brad Holister , Carl K. Mizuyabu
IPC分类号： G06F1206
CPC分类号： H04N19/423
摘要： A method and apparatus for storing sequential data words associated with a block of data in a non-linear manner within the data block is taught such that any row or column associated with the data block may be accessed using a burst access. A row, or column of data accessed by a burst frees up instruction bandwidth of a video controller. In particular, it is assured that each row and column of data associated with the data block has at least one sequential pair of data words associated with it. By assuring at least one sequential pair of data words, it is possible to issue a burst request for a minimum of two words of data with each row access, or column access of the video controller.
摘要翻译：教导以数据块中的非线性方式存储与数据块相关联的顺序数据字的方法和装置，使得可以使用突发存取来访问与数据块相关联的任何行或列。由突发访问的一行或一列数据释放视频控制器的指令带宽。特别地，确保与数据块相关联的每一行和数据列具有与其相关联的至少一个连续数据字对。通过确保至少一个顺序的数据字对，可以对视频控制器的每一行访问或列访问发出至少两个数据字的突发请求。

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