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1. 发明申请

US20040007738A1 Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same 有权
标题翻译： FinFET应用的自对准狗骨结构及其制造方法
公开(公告)号：US20040007738A1
公开(公告)日：2004-01-15
申请号：US10428705
申请日：2003-05-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： David M. Fried , Timothy J. Hoague , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78636
摘要： A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a source region and a drain region. The channel region has a first horizontal width and the source and drain regions having a second horizontal width that is greater than the first horizontal width. Each of the source and drain regions have tapered portions abutting the channel region with a horizontal width that varies in a substantially linear manner from the first horizontal width to the second horizontal width.
摘要翻译：提供了具有自对准狗骨结构的垂直取向的FET及其制造方法。具体地，垂直取向的FET包括沟道区，源极区和漏极区。沟道区具有第一水平宽度，并且源区和漏区具有大于第一水平宽度的第二水平宽度。源极和漏极区域中的每一个具有与沟道区域邻接的具有从第一水平宽度到第二水平宽度基本线性地变化的水平宽度的锥形部分。

2. 发明申请

US20030141548A1 HIGH MOBILITY TRANSISTORS IN SOI AND METHOD FOR FORMING 有权
标题翻译： SOI中的高移动晶体管和形成方法
公开(公告)号：US20030141548A1
公开(公告)日：2003-07-31
申请号：US09683656
申请日：2002-01-30
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Xavier Baie , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L027/01 , H01L027/12 , H01L031/0392
CPC分类号： H01L29/7842 , H01L21/84 , H01L27/1203
摘要： The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.
摘要翻译：本发明提供了一种用于形成场效应晶体管（FET）的器件设计和方法，其具有改进的性能而不会对器件密度造成负面影响。本发明通过在硅岛上形成高增益p沟道晶体管，其中空穴迁移率已经增加。通过对硅岛施加物理应变来增加空穴迁移率。通过拉伸硅岛，空穴迁移率增加，导致器件增益增加。这是在不需要增加设备尺寸或者与设备的触点的尺寸的情况下实现的。

3. 发明申请

US20030141543A1 Body contact mosfet 有权
标题翻译：身体接触mosfet
公开(公告)号：US20030141543A1
公开(公告)日：2003-07-31
申请号：US10061263
申请日：2002-01-31
申请人： International Business Machines Corporation
发明人： Andres Bryant , Peter E. Cottrell , John J. Ellis-Monaghan , Robert J. Gauthier JR. , Edward J. Nowak , Jed H. Rankin , Fariborz Assaderaghi
IPC分类号： H01L027/01 , H01L027/12 , H01L029/76 , H01L029/94
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.
摘要翻译：公开了一种在有源区的主体接触部分和有源区的晶体管部分之间利用绝缘结构的体接触结构。在一个实施例中，本发明将绝缘体替代晶体管和身体接触之间的区域中的栅极层的至少一部分。在另一个实施例中，栅极层的一部分被去除并且在晶体管和身体接触之间的区域中被绝缘层替代。在另一个实施例中，通过在晶体管和身体接触之间的区域中在栅极和主体之间形成多个栅极电介质层来形成绝缘结构。通过这些方法产生的身体接触对栅极没有增加显着的栅极电容。

4. 发明申请

US20020140039A1 Double gate trench transistor 失效
公开(公告)号：US20020140039A1
公开(公告)日：2002-10-03
申请号：US10064171
申请日：2002-06-18
申请人： International Business Machines Corporation
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
IPC分类号： H01L029/76
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66818
摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

5. 发明申请

US20040222488A1 HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION 失效
标题翻译：具有低温分离区域的高电压N-LDMOS晶体管
公开(公告)号：US20040222488A1
公开(公告)日：2004-11-11
申请号：US10249766
申请日：2003-05-06
申请人： International Business Machines Corporation
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Robert J. Gauthier JR. , Jed H. Rankin , William R. Tonti
IPC分类号： H01L029/00
CPC分类号： H01L29/0878 , H01L21/26586 , H01L21/266 , H01L29/0653 , H01L29/086 , H01L29/42368 , H01L29/66689 , H01L29/7816
摘要： A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.
摘要翻译：公开了一种用于晶体管的方法和结构，该晶体管具有栅极，栅极下方的沟道区，沟道区一侧的源极区，与源极区沟道区相反侧的漏极区，浅沟槽在漏极区和沟道区之间的衬底中的隔离（STI）区，以及在STI区之下的漏极延伸。漏极延伸沿着STI区域的底部并沿着STI的边的一部分定位。沿着STI底部的漏极延伸部分可以包括不同于沿着STI侧面的漏极延伸部分的掺杂剂注入。沿着STI侧面的排水延伸部分从STI的底部延伸到部分沿着STI侧面的位置。 STI区域位于栅极的一部分之下。漏极延伸部在漏极区域和围绕STI的下周边的沟道区域之间提供导电路径。漏极区域比源极区域更靠近栅极定位。

6. 发明申请

US20030080383A1 Active well schemes for SOI technology 失效
公开(公告)号：US20030080383A1
公开(公告)日：2003-05-01
申请号：US10205528
申请日：2002-07-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： William F. Clark JR. , Edward J. Nowak , Jed H. Rankin , Minh H. Tong
IPC分类号： H01L021/00
CPC分类号： H01L29/66772 , H01L21/743 , H01L29/66545 , H01L29/78612 , H01L29/78618 , Y10S148/077 , Y10S148/15
摘要： A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.

7. 发明申请

US20030057486A1 Fin field effect transistor with self-aligned gate 有权
标题翻译：具有自对准栅极的Fin场效应晶体管
公开(公告)号：US20030057486A1
公开(公告)日：2003-03-27
申请号：US09965288
申请日：2001-09-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey P. Gambino , Jerome B. Lasky , Jed H. Rankin
IPC分类号： H01L027/01 , H01L027/12 , H01L031/0392
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78636
摘要： The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.
摘要翻译：本发明提供一种用于制造具有双栅极和双通道的金属氧化物半导体场效应晶体管（MOSFET）的方法，其中栅极区域与沟道区域和源极/漏极扩散接合点自对准。本发明还涉及使用本发明的方法形成的FIN MOSFFET结构。

8. 发明申请

US20040004268A1 E-Fuse and anti-E-Fuse device structures and methods 审中-公开
标题翻译：电子熔断器和反电子保险丝器件的结构和方法
公开(公告)号：US20040004268A1
公开(公告)日：2004-01-08
申请号：US10064376
申请日：2002-07-08
申请人： International Business Machines Corporation
发明人： Jeffrey S. Brown , Robert J. Gauthier JR. , Jed H. Rankin , William R. Tonti
IPC分类号： H01L029/00
CPC分类号： H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods. Each of the three methods can be used with three different embodiments, a first embodiment is a polysilicon E-Fuse with a sub-minimum width polysilicon fuse line, a second embodiment is a work function altered/programmed self-aligned MOSFET E-Fuse with a sub-minimum width fuse line, and a third embodiment is a polysilicon MOSFET E-Fuse with a sub-minimum width fuse line which is programmed with a low trigger voltage snapback.
摘要翻译：使用标准光刻法来图案化和制造最终的多晶硅晶片成像结构，该结构小于正常允许光刻最小尺寸。提供了三种不同的方法来产生这样的次最小维度结构，第一种方法使用具有掩模的最小尺寸图案特征之间的亚最小空间的光刻掩模，第二种方法使用光刻掩模与次最小宽度方向点动或掩模的最小尺寸图案特征之间的偏移，第三种方法是第一和第二方法的组合。三种方法中的每一种可以与三种不同的实施例一起使用，第一实施例是具有亚最小宽度多晶硅熔丝线的多晶硅E熔丝，第二实施例是工作功能改变/编程的自对准MOSFET E-Fuse，具有亚最小宽度熔丝线，第三实施例是具有低电平触发电压快速编程的亚最小宽度熔丝线的多晶硅MOSFET E-Fuse。

9. 发明申请

US20030165705A1 Method of forming refractory metal contact in an opening, and resulting structure 失效
$Method of forming refractory metal contact in an opening, and resulting structure$
标题翻译：在开口中形成难熔金属接触的方法，以及结果
公开(公告)号：US20030165705A1
公开(公告)日：2003-09-04
申请号：US09826036
申请日：2001-04-04
申请人： International Business Machines Corporation
发明人： Jonathan D. Chapple-Sokol , Randy W. Mann , William J. Murphy , Jed H. Rankin , Daniel S. Vanslette
IPC分类号： C23C016/00 , B05D001/36
CPC分类号： C23C28/00 , Y10T428/12
摘要： A method of ensuring against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 null, serves a sacrificial purpose and prevents interaction between any fluorine that is released during the refractory material deposition step from interacting with the underlying silicide.
摘要翻译：通过首先在耐火材料沉积之前提供连续的多晶硅层，来实现通过物理气相沉积（PVD）或化学气相沉积（CVD）确保耐蚀材料层沉积在其下的硅化物层的劣化的方法。连续多晶硅层，优选不大于50，用于牺牲目的，并且防止在耐火材料沉积步骤期间释放的任何氟与下面的硅化物相互作用的相互作用。

10. 发明申请

US20020153587A1 Double planar gated SOI MOSFET structure 失效
公开(公告)号：US20020153587A1
公开(公告)日：2002-10-24
申请号：US10064318
申请日：2002-07-02
申请人： International Business Machines Corporation
发明人： James W. Adkisson , John A. Bracchitta , John J. Ellis-Monaghan , Jerome B. Lasky , Effendi Leobandung , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L021/00
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66545 , H01L29/66795
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

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