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1. 发明申请

US20040251496A1 ZERO THRESHOLD VOLTAGE PFET AND METHOD OF MAKING SAME 失效
标题翻译：零阈值电压PFET及其制造方法
公开(公告)号：US20040251496A1
公开(公告)日：2004-12-16
申请号：US10250190
申请日：2003-06-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey S. Brown , Chung H. Lam , Randy W. Mann , Jeffrey H. Oppold
IPC分类号： H01L029/76
CPC分类号： H01L29/1037 , H01L21/823412 , H01L21/823493 , H01L29/78
摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116null) and then annealing the substrate so as to cause the regions of the lower portion (140null) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
摘要翻译：零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与彼此隔开p型衬底材料的口袋。在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。

2. 发明申请

US20030020116A1 Grounded body SOI SRAM cell 有权
公开(公告)号：US20030020116A1
公开(公告)日：2003-01-30
申请号：US09915061
申请日：2001-07-25
申请人： International Business Machines Corporation
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier JR. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L021/00 , H01L021/84
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.

3. 发明申请

US20040000685A1 STRUCTURE FOR SCALABLE, LOW-COST POLYSILICON DRAM IN A PLANAR CAPAACITOR 失效
标题翻译：在平面电容器中可扩展的低成本多晶硅DRAM的结构
公开(公告)号：US20040000685A1
公开(公告)日：2004-01-01
申请号：US10064301
申请日：2002-07-01
申请人： International Business Machines Corporation
发明人： Jeffrey S. Brown , Randy W. Mann
IPC分类号： H01L021/8234 , H01L021/8244
CPC分类号： H01L27/10861 , H01L27/0207 , H01L27/1203
摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.
摘要翻译：提供了增加电容而不损及电池区的电容器结构及其制造方法。第一电容器结构包括存在于半导体衬底中的孔中的绝缘材料，其中每个电容器孔的底壁上的绝缘材料与每个孔的侧壁相比较厚。在另一个电容器结构中，提供深电容器孔，其具有存在于每个孔下方的隔离植入区。

4. 发明申请

US20030141548A1 HIGH MOBILITY TRANSISTORS IN SOI AND METHOD FOR FORMING 有权
标题翻译： SOI中的高移动晶体管和形成方法
公开(公告)号：US20030141548A1
公开(公告)日：2003-07-31
申请号：US09683656
申请日：2002-01-30
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Xavier Baie , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L027/01 , H01L027/12 , H01L031/0392
CPC分类号： H01L29/7842 , H01L21/84 , H01L27/1203
摘要： The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.
摘要翻译：本发明提供了一种用于形成场效应晶体管（FET）的器件设计和方法，其具有改进的性能而不会对器件密度造成负面影响。本发明通过在硅岛上形成高增益p沟道晶体管，其中空穴迁移率已经增加。通过对硅岛施加物理应变来增加空穴迁移率。通过拉伸硅岛，空穴迁移率增加，导致器件增益增加。这是在不需要增加设备尺寸或者与设备的触点的尺寸的情况下实现的。

5. 发明申请

US20030102518A1 Finfet SRAM cell using low mobility plane for cell stability and method for forming 有权
标题翻译： Finfet SRAM单元使用低迁移率平面进行电池稳定性和形成方法
公开(公告)号：US20030102518A1
公开(公告)日：2003-06-05
申请号：US10011351
申请日：2001-12-04
申请人： International Business Machines Corporation
发明人： David M. Fried , Randy W. Mann , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L029/76
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the null110null plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the null100null. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation
摘要翻译：本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作

6. 发明申请

US20040251475A1 Zero threshold voltage pFET and method of making same 失效
标题翻译：零阈值电压pFET及其制作方法
公开(公告)号：US20040251475A1
公开(公告)日：2004-12-16
申请号：US10845835
申请日：2004-05-14
申请人： International Business Machines Corporation
发明人： Jeffrey S. Brown , Chung H. Lam , Randy W. Mann , Jeffery H. Oppold
IPC分类号： H01L029/76
CPC分类号： H01L29/1037 , H01L21/823412 , H01L21/823493 , H01L29/78
摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116null) and then annealing the substrate so as to cause the regions of the lower portion (140null) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
摘要翻译：零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与彼此隔开p型衬底材料的口袋。在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。

7. 发明申请

US20040001376A1 Method and design for measuring SRAM array leakage macro (ALM) 失效
公开(公告)号：US20040001376A1
公开(公告)日：2004-01-01
申请号：US10064302
申请日：2002-07-01
申请人： International Business Machines Corporation
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffery H. Oppold
IPC分类号： G11C029/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.

8. 发明申请

US20030165705A1 Method of forming refractory metal contact in an opening, and resulting structure 失效
$Method of forming refractory metal contact in an opening, and resulting structure$
标题翻译：在开口中形成难熔金属接触的方法，以及结果
公开(公告)号：US20030165705A1
公开(公告)日：2003-09-04
申请号：US09826036
申请日：2001-04-04
申请人： International Business Machines Corporation
发明人： Jonathan D. Chapple-Sokol , Randy W. Mann , William J. Murphy , Jed H. Rankin , Daniel S. Vanslette
IPC分类号： C23C016/00 , B05D001/36
CPC分类号： C23C28/00 , Y10T428/12
摘要： A method of ensuring against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 null, serves a sacrificial purpose and prevents interaction between any fluorine that is released during the refractory material deposition step from interacting with the underlying silicide.
摘要翻译：通过首先在耐火材料沉积之前提供连续的多晶硅层，来实现通过物理气相沉积（PVD）或化学气相沉积（CVD）确保耐蚀材料层沉积在其下的硅化物层的劣化的方法。连续多晶硅层，优选不大于50，用于牺牲目的，并且防止在耐火材料沉积步骤期间释放的任何氟与下面的硅化物相互作用的相互作用。

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