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1. 发明授权

US06169693A Self-convergence of post-erase threshold voltages in a flash memory cell using transient response 有权
标题翻译：使用瞬态响应的闪存单元中擦除后阈值电压的自收敛
公开(公告)号：US06169693A
公开(公告)日：2001-01-02
申请号：US09429239
申请日：1999-10-28
申请人： I-Chuin Peter Chan , Feng Frank Qian , Hsingya Arthur Wang
发明人： I-Chuin Peter Chan , Feng Frank Qian , Hsingya Arthur Wang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/14 , G11C16/3404
摘要： An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.
摘要翻译：擦除方法通过在沟道区域中存在横向场的情况下快速切换控制栅极上的偏置来在快闪存储器单元上提供自会聚擦除。优选地，通过对电池的源极和漏极进行差分偏置来提供横向场，并且控制栅极的偏置变化足够快以在浮动栅极处引起瞬态响应。在通道区域和浮置栅极之间穿过隧穿氧化物的跨瞬时垂直场引起在通道区域和浮动栅极之间引起适度的热载流子注入。这种方法是自会聚的，因为除非在阵列步骤期间从浮置栅极去除足够数量的载流子，否则不会发生对浮栅的载流子注入。由于自会聚效应的大部分是随着控制栅极电压的转变而在其后不久发生的，所以在擦除脉冲结束时需要很少的时间来实现该响应。

2. 发明授权

US6026026A Self-convergence of post-erase threshold voltages in a flash memory cell using transient response 失效
标题翻译：使用瞬态响应的闪存单元中擦除后阈值电压的自收敛
公开(公告)号：US6026026A
公开(公告)日：2000-02-15
申请号：US985833
申请日：1997-12-05
申请人： I-Chuin Peter Chan , Feng Frank Qian , Hsingya Arthur Wang
发明人： I-Chuin Peter Chan , Feng Frank Qian , Hsingya Arthur Wang
IPC分类号： G11C16/14 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3409 , G11C16/14 , G11C16/3404
摘要： An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.
摘要翻译：擦除方法通过在沟道区域中存在横向场的情况下快速切换控制栅极上的偏置来在快闪存储器单元上提供自会聚擦除。优选地，通过对电池的源极和漏极进行差分偏置来提供横向场，并且控制栅极的偏置变化足够快以在浮动栅极处引起瞬态响应。在通道区域和浮置栅极之间穿过隧穿氧化物的跨瞬时垂直场引起在通道区域和浮动栅极之间引起适度的热载流子注入。这种方法是自会聚的，因为除非在阵列步骤期间从浮置栅极去除足够数量的载流子，否则不会发生对浮栅的载流子注入。由于自会聚效应的大部分是随着控制栅极电压的转变而在其后不久发生的，所以在擦除脉冲结束时需要很少的时间来实现该响应。

3. 发明授权

US07250341B2 Flash memory device having poly spacers 失效
标题翻译：具有聚间隔物的闪存器件
公开(公告)号：US07250341B2
公开(公告)日：2007-07-31
申请号：US11100123
申请日：2005-04-05
申请人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
发明人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.
摘要翻译：非易失性存储器件包括具有第一有源区和第二有源区的衬底。第一浮动栅极设置在第一有源区上并具有边缘，第一浮栅由导电材料制成。第一间隔件连接到第一浮栅的边缘并由与第一浮栅相同的导电材料制成。控制门靠近浮动栅极设置。

4. 发明授权

US06777741B2 Non-volatile memory cells with selectively formed floating gate 失效
标题翻译：具有选择性形成的浮动栅极的非易失性存储单元
公开(公告)号：US06777741B2
公开(公告)日：2004-08-17
申请号：US10393603
申请日：2003-03-19
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.
摘要翻译：提供了非易失性存储晶体管，其包括由第一和第二层材料（例如多晶硅）形成的浮置栅极。第二浮栅层选择性地生长或沉积在第一栅极层的顶部上，消除了对第二浮栅层定位的掩模的需要。存储晶体管由隔离区域分隔开。第二浮栅层与隔离区域的一部分重叠以提供高控制栅 - 浮栅耦合比。该过程使更小的存储晶体管。浮栅为隔离重叠，因此浮栅为浮栅间隔，通过第二多晶硅层的选择性沉积或选择性外延生长来控制。

5. 发明授权

US6043123A Triple well flash memory fabrication process 失效
标题翻译：三重闪存制造工艺
公开(公告)号：US6043123A
公开(公告)日：2000-03-28
申请号：US863917
申请日：1997-05-27
申请人： Hsingya Arthur Wang , Jein-Chen Young , Ming-Sang Kwan
发明人： Hsingya Arthur Wang , Jein-Chen Young , Ming-Sang Kwan
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546
摘要： A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.
摘要翻译：描述了在半导体衬底中制造集成电路存储器的过程。在衬底中，通过引入与衬底的导电性相反的掺杂剂形成第一阱。在第一阱内，第二阱由与衬底相匹配的导电类型形成。存储单元被制造在第二阱中并且具有与导电类型衬底相对的源区和漏区。第一和第二孔中的每一个还包括相应导电类型的区域，以使得能够对每个孔进行单独的电连接。

6. 发明授权

US5981364A Method of forming a silicon gate to produce silicon devices with improved performance 失效
标题翻译：形成硅栅极以产生具有改进性能的硅器件的方法
公开(公告)号：US5981364A
公开(公告)日：1999-11-09
申请号：US568195
申请日：1995-12-06
申请人： Mark T. Ramsbey , Hsingya Arthur Wang , Yu Sun
发明人： Mark T. Ramsbey , Hsingya Arthur Wang , Yu Sun
IPC分类号： H01L21/28 , H01L29/49
CPC分类号： H01L21/28035 , H01L29/4925
摘要： Disclosed herein is a method of forming a silicon gate stack onto a silicon substrate for a silicon device. The method of forming the silicon gate stack comprises the steps of growing an oxide layer onto the silicon substrate, depositing a thin layer of silicon to form a thin layer of silicon over the oxide layer, depositing a thick layer of silicon over the thin layer of silicon, and introducing impurities into only the thick layer of silicon to form a silicon gate whereby the silicon gate includes the thin layer of silicon and the thick layer of silicon having the impurities. The impurities being introduced with a concentration, the impurities concentration and the thick layer thickness impeding an encroachment by the oxide layer into the silicon gate during application of a protective screen oxide layer around the silicon gate stack.
摘要翻译：本文公开了一种在硅器件的硅衬底上形成硅栅叠层的方法。形成硅栅极堆叠的方法包括以下步骤：在硅衬底上生长氧化物层，沉积薄层的硅以在氧化物层上形成薄的硅层，在薄层上沉积厚的硅层硅，并且将杂质引入仅硅的厚层中以形成硅栅极，由此硅栅极包括硅的薄层和具有杂质的厚的硅层。引入浓度的杂质，杂质浓度和厚层厚度在施加硅栅堆叠周围的保护性屏蔽氧化物层时阻碍氧化层侵入硅栅中。

7. 发明授权

US5776811A Simplified process for fabricating flash eeprom cells 失效
标题翻译：制造闪光电池的简化过程
公开(公告)号：US5776811A
公开(公告)日：1998-07-07
申请号：US582720
申请日：1996-01-04
申请人： Hsingya Arthur Wang , Jian Chen , Paul J. Steffan
发明人： Hsingya Arthur Wang , Jian Chen , Paul J. Steffan
IPC分类号： H01L21/336 , H01L29/788 , H01L21/8247
CPC分类号： H01L29/66825 , H01L29/7885
摘要： A simplified fabrication procedure for making flash EEPROM memory cells is disclosed. The method comprises performing a double-diffuse (deep) junction implant after the shallow source/drain of the memory cell have been implanted and formed. A high energy double-diffuse implant is used to replace separate, individual implant and diffusion steps which results in a memory cell having, less damage to its substrate.
摘要翻译：公开了一种用于制造快速EEPROM存储单元的简化制造程序。该方法包括在已经注入和形成存储单元的浅源极/漏极之后执行双扩散（深）结注入。高能双漫射植入物被用于代替单独的个体注入和扩散步骤，导致记忆单元对其底物的损伤较小。

8. 发明授权

US08288219B2 Method of forming a non-volatile memory cell using off-set spacers 有权
标题翻译：使用偏置间隔物形成非易失性存储单元的方法
公开(公告)号：US08288219B2
公开(公告)日：2012-10-16
申请号：US12052374
申请日：2008-03-20
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A stack of two polysilicon layers is formed over a semiconductor body region. A DDD implant is performed to form a DDD source region in the semiconductor body region along a source side of the polysilicon stack but not along a drain side of the polysilicon stack. Off-set spacers are formed along opposing side-walls of the polysilicon stack. A source/drain implant is performed to form a drain region in the semiconductor body region along the drain side of the polysilicon stack and to form a highly doped region within the DDD source region such that the extent of an overlap between the polysilicon stack and each of the drain region and the highly doped region is inversely dependent on a thickness of the off-set spacers, and a lateral spacing directly under the polysilicon stack between adjacent edges of the DDD source region and the highly doped region is directly dependent on the thickness of the off-set spacers.
摘要翻译：在半导体主体区域上形成一叠两层多晶硅层。执行DDD注入以在半导体主体区域中沿着多晶硅堆叠的源极侧形成DDD源极区域，但不沿着多晶硅叠层的漏极侧。偏移间隔物沿着多晶硅堆叠的相对侧壁形成。进行源极/漏极注入以沿着多晶硅堆叠的漏极侧在半导体主体区域中形成漏极区域，并且在DDD源极区域内形成高度掺杂的区域，使得多晶硅堆叠和每个漏极区域和高掺杂区域的反向取决于偏置间隔物的厚度，并且在DDD源极区域和高度掺杂区域的相邻边缘之间直接在多晶硅堆叠下面的横向间隔直接取决于厚度的偏置间隔物。

9. 发明授权

US07202134B2 Method of forming transistors with ultra-short gate feature 有权
标题翻译：具有超短栅极特性的晶体管形成方法
公开(公告)号：US07202134B2
公开(公告)日：2007-04-10
申请号：US11022005
申请日：2004-12-21
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a LDD implant is carried out to from LDD source and drain regions in the body region for the second transistor. After the LDD implant, main spacers are formed adjacent the off-set spacers of at least the second transistor. After forming the main spacers, a source/drain implant is carried out to form a highly doped region within each of the DDD drain and source regions and the LDD drain and source regions.
摘要翻译：对于第一和第二晶体管中的每一个，栅电极形成在半导体本体区域的绝缘上。从DDD源和DDD漏极区域对第一晶体管进行DDD注入。在DDD植入之后，沿着第一和第二晶体管的每一个的栅电极的侧壁形成偏置间隔物。在形成偏置间隔物之后，从第二晶体管的体区中的LDD源极和漏极区域执行LDD注入。在LDD注入之后，主间隔物形成在至少第二晶体管的偏置间隔物附近。在形成主间隔物之后，进行源极/漏极注入以在每个DDD漏极和源极区域以及LDD漏极和源极区域内形成高掺杂区域。

10. 发明申请

US20050186739A1 Flash memory device having poly spacers 失效
公开(公告)号：US20050186739A1
公开(公告)日：2005-08-25
申请号：US11100123
申请日：2005-04-05
申请人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
发明人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.

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