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1. 发明授权

US07576395B2 Dual gate stack CMOS structure with different dielectrics 有权
标题翻译：具有不同电介质的双栅叠层CMOS结构
公开(公告)号：US07576395B2
公开(公告)日：2009-08-18
申请号：US11044968
申请日：2005-01-27
申请人： Hyung-Suk Jung , Jong-Ho Lee , Hwa-Sung Rhee , Jae-Kwang Choi
发明人： Hyung-Suk Jung , Jong-Ho Lee , Hwa-Sung Rhee , Jae-Kwang Choi
IPC分类号： H01L23/62
CPC分类号： H01L21/823857 , H01L21/28194 , H01L21/3141 , H01L21/31608 , H01L21/31645 , H01L21/823842 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.
摘要翻译：集成电路器件包括具有第一掺杂区域和具有与第一掺杂区域不同的掺杂类型的第二掺杂区域的半导体衬底。半导体衬底上的栅极电极结构在第一和第二掺杂区域之间延伸，并且在第一掺杂区域中具有第一高介电常数材料的栅极绝缘层和不同于第一高介电常数的第二高介电常数材料材料，在第二掺杂区域。栅极电极位于栅极绝缘层上。

2. 发明申请

US20060003507A1 Integrated circuit devices including a dual gate stack structure and methods of forming the same 有权
标题翻译：集成电路器件，包括双栅叠层结构及其形成方法
公开(公告)号：US20060003507A1
公开(公告)日：2006-01-05
申请号：US11044968
申请日：2005-01-27
申请人： Hyung-Suk Jung , Jong-Ho Lee , Hwa-Sung Rhee , Jae-Kwang Choi
发明人： Hyung-Suk Jung , Jong-Ho Lee , Hwa-Sung Rhee , Jae-Kwang Choi
IPC分类号： H01L21/336
CPC分类号： H01L21/823857 , H01L21/28194 , H01L21/3141 , H01L21/31608 , H01L21/31645 , H01L21/823842 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.
摘要翻译：集成电路器件包括具有第一掺杂区域和具有与第一掺杂区域不同的掺杂类型的第二掺杂区域的半导体衬底。半导体衬底上的栅极电极结构在第一和第二掺杂区域之间延伸，并且在第一掺杂区域中具有第一高介电常数材料的栅极绝缘层和不同于第一高介电常数的第二高介电常数材料材料，在第二掺杂区域。栅极电极位于栅极绝缘层上。

3. 发明授权

US08252674B2 Transistors with multilayered dielectric films and methods of manufacturing such transistors 有权
标题翻译：具有多层介电膜的晶体管和制造这种晶体管的方法
公开(公告)号：US08252674B2
公开(公告)日：2012-08-28
申请号：US13195935
申请日：2011-08-02
申请人： Ha-Jin Lim , Jong-Ho Lee , Hyung-Suk Jung
发明人： Ha-Jin Lim , Jong-Ho Lee , Hyung-Suk Jung
IPC分类号： H01L21/3205
CPC分类号： H01L21/28185 , H01L21/28079 , H01L21/28194 , H01L21/28202 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517
摘要： Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.
摘要翻译：提供了在通道区域上包括多层电介质膜的晶体管。多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。在多层电介质膜上设置栅电极。

4. 发明授权

US07586159B2 Semiconductor devices having different gate dielectrics and methods for manufacturing the same 有权
标题翻译：具有不同栅极电介质的半导体器件及其制造方法
公开(公告)号：US07586159B2
公开(公告)日：2009-09-08
申请号：US11723705
申请日：2007-03-21
申请人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
发明人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L27/0922
摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
摘要翻译：半导体器件包括第一和第二晶体管器件。第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。第一栅极电介质位于第一衬底区域和第一栅电极之间。第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。第二栅极电介质位于第二基板区域和第二栅极电极之间。第一栅极电介质包括介电常数为8以上的第一高k层。类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。第二高k层具有与第一高k层不同的材料组成。

5. 发明申请

US20070176242A1 Semiconductor devices having different gate dielectrics and methods for manufacturing the same 有权
标题翻译：具有不同栅极电介质的半导体器件及其制造方法
公开(公告)号：US20070176242A1
公开(公告)日：2007-08-02
申请号：US11723705
申请日：2007-03-21
申请人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
发明人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L27/0922
摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
摘要翻译：半导体器件包括第一和第二晶体管器件。第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。第一栅极电介质位于第一衬底区域和第一栅电极之间。第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。第二栅极电介质位于第二基板区域和第二栅极电极之间。第一栅极电介质包括介电常数为8以上的第一高k层。类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。第二高k层具有与第一高k层不同的材料组成。

6. 发明申请

US20070001241A1 Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same 有权
标题翻译：具有氮结合有源区的半导体器件及其制造方法
公开(公告)号：US20070001241A1
公开(公告)日：2007-01-04
申请号：US11396702
申请日：2006-04-04
申请人： Ha-Jin Lim , Jong-Ho Lee , Hyung-Suk Jung , Yun Kim , Min Kim
发明人： Ha-Jin Lim , Jong-Ho Lee , Hyung-Suk Jung , Yun Kim , Min Kim
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823857
摘要： A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.
摘要翻译：半导体器件可以包括具有第一区域和第二区域的半导体衬底。可以在第一区域内形成含氮的有源区。可以在引入氮的有源区上形成第一栅电极。第一栅极电介质层可插入在引入氮的有源区和第一栅电极之间。第一栅介质层可以包括第一介电层和第二介电层。第二电介质层可以是含氮介电层。第二栅极电极可以形成在第二区域上。可以在第二区域和第二栅电极之间插入第二栅极电介质层。第一栅极介电层可以具有与第二栅极介电层相同或基本相同的厚度，并且含氮介电层可以与引入氮的有源区接触。

7. 发明申请

US20060115940A1 Dual work function metal gate structure and related method of manufacture 有权
公开(公告)号：US20060115940A1
公开(公告)日：2006-06-01
申请号：US11192288
申请日：2005-07-29
申请人： Min-Joo Kim , Hyung-Suk Jung , Jong-Ho Lee , Sungkee Han
发明人： Min-Joo Kim , Hyung-Suk Jung , Jong-Ho Lee , Sungkee Han
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/28088 , H01L21/823842
摘要： A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine.

8. 发明申请

US20050148127A1 Semiconductor device including gate dielectric layer formed of high dielectric alloy and method of fabricating the same 审中-公开
标题翻译：包括由高介电合金形成的栅极介电层的半导体器件及其制造方法
公开(公告)号：US20050148127A1
公开(公告)日：2005-07-07
申请号：US10989200
申请日：2004-11-15
申请人： Hyung-Suk Jung , Jong-Ho Lee , Seok-Joo Doh , Yun-Seok Kim
发明人： Hyung-Suk Jung , Jong-Ho Lee , Seok-Joo Doh , Yun-Seok Kim
IPC分类号： H01L21/336 , H01L21/28 , H01L29/51
CPC分类号： H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device is disclosed comprising an improved gate dielectric layer formed of a high dielectric alloy-like composite together with a method for fabricating the same. The semiconductor device comprises a semiconductor substrate and a gate dielectric layer consisting essentially of a high-k alloy-like composite containing a first element, a second element, and oxygen (O). The first element is at least one member selected from a first group consisting of Al, La, Y, Ga, and In. The second element is at least one member selected from a second group consisting of Hf, Zr, and Ti. A diffusion barrier is formed on the gate dielectric layer, and a gate is formed on the diffusion barrier.
摘要翻译：公开了一种半导体器件，其包括由高介电合金样复合材料形成的改进的栅介质层及其制造方法。半导体器件包括半导体衬底和基本上由含有第一元素，第二元素和氧（O）的高k合金样复合材料组成的栅极电介质层。第一元素是选自由Al，La，Y，Ga和In组成的第一组中的至少一种。第二元素是选自由Hf，Zr和Ti构成的第二组中的至少一种。在栅介电层上形成扩散阻挡层，在扩散阻挡层上形成栅极。

9. 发明授权

US07829953B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07829953B2
公开(公告)日：2010-11-09
申请号：US11966640
申请日：2007-12-28
申请人： Hyung Suk Jung , Jong-Ho Lee , Sung Kee Han , Ha Jin Lim
发明人： Hyung Suk Jung , Jong-Ho Lee , Sung Kee Han , Ha Jin Lim
IPC分类号： H01L29/72
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823857 , H01L27/0922 , H01L29/20 , H01L29/22 , H01L29/24 , H01L29/49 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, a gate insulating layer formed on the semiconductor substrate, an NMOS gate formed on the gate insulating layer of the NMOS region, and a PMOS gate formed on the gate insulating layer of the PMOS region. Any one of the NMOS gate and the PMOS gate includes a one-layered conductive layer pattern, and another of the NMOS gate and the PMOS gate includes a three-layered conductive layer pattern.
摘要翻译：半导体器件包括：包括NMOS区域和PMOS区域的半导体衬底;形成在半导体衬底上的栅极绝缘层;形成在NMOS区域的栅极绝缘层上的NMOS栅极;以及栅极绝缘层上形成的PMOS栅极; 的PMOS区域。 NMOS栅极和PMOS栅极中的任何一个包括单层导电层图案，NMOS栅极和PMOS栅极中的另一个包括三层导电层图案。

10. 发明申请

US20100025781A1 Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors 有权
标题翻译：具有多层介质膜的晶体管及其制造方法
公开(公告)号：US20100025781A1
公开(公告)日：2010-02-04
申请号：US12574912
申请日：2009-10-07
申请人： Ha-Jin Lim , Jong-Ho Lee , Hyung-Suk Jung
发明人： Ha-Jin Lim , Jong-Ho Lee , Hyung-Suk Jung
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/28079 , H01L21/28194 , H01L21/28202 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517
摘要： Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.
摘要翻译：提供了在通道区域上包括多层电介质膜的晶体管。多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。在多层电介质膜上设置栅电极。

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