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1. 发明授权

US07494940B2 Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices 有权
标题翻译：在集成电路器件中在界面层上形成高介电层的后热处理方法
公开(公告)号：US07494940B2
公开(公告)日：2009-02-24
申请号：US11333741
申请日：2006-01-17
申请人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02323 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3143 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
摘要翻译：可以将通过氧化，退火，氧化，氧化，氧化，氧化，氧化钇和/或其他金属氧化物和/或硅衬底上的其它金属氧化物和硅酸盐形成的高介电层氮化和后热处理，或氧化和退火的组合以形成具有优异迁移率和界面特性的高介电层。

2. 发明申请

US20060115993A1 Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices 有权
公开(公告)号：US20060115993A1
公开(公告)日：2006-06-01
申请号：US11333741
申请日：2006-01-17
申请人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02323 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3143 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

3. 发明申请

US20050098839A1 Semiconductor devices having different gate dielectrics and methods for manufacturing the same 审中-公开
标题翻译：具有不同栅极电介质的半导体器件及其制造方法
公开(公告)号：US20050098839A1
公开(公告)日：2005-05-12
申请号：US10930943
申请日：2004-09-01
申请人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
发明人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/94
CPC分类号： H01L21/823857
摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
摘要翻译：半导体器件包括第一和第二晶体管器件。第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。第一栅极电介质位于第一衬底区域和第一栅电极之间。第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。第二栅极电介质位于第二基板区域和第二栅极电极之间。第一栅极电介质包括介电常数为8以上的第一高k层。类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。第二高k层具有与第一高k层不同的材料组成。

4. 发明授权

US07586159B2 Semiconductor devices having different gate dielectrics and methods for manufacturing the same 有权
标题翻译：具有不同栅极电介质的半导体器件及其制造方法
公开(公告)号：US07586159B2
公开(公告)日：2009-09-08
申请号：US11723705
申请日：2007-03-21
申请人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
发明人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L27/0922
摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
摘要翻译：半导体器件包括第一和第二晶体管器件。第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。第一栅极电介质位于第一衬底区域和第一栅电极之间。第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。第二栅极电介质位于第二基板区域和第二栅极电极之间。第一栅极电介质包括介电常数为8以上的第一高k层。类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。第二高k层具有与第一高k层不同的材料组成。

5. 发明申请

US20070176242A1 Semiconductor devices having different gate dielectrics and methods for manufacturing the same 有权
标题翻译：具有不同栅极电介质的半导体器件及其制造方法
公开(公告)号：US20070176242A1
公开(公告)日：2007-08-02
申请号：US11723705
申请日：2007-03-21
申请人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
发明人： Jong-Ho Lee , Ho-Kyu Kang , Yun-Seok Kim , Seok-Joo Doh , Hyung-Suk Jung
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L27/0922
摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
摘要翻译：半导体器件包括第一和第二晶体管器件。第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。第一栅极电介质位于第一衬底区域和第一栅电极之间。第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。第二栅极电介质位于第二基板区域和第二栅极电极之间。第一栅极电介质包括介电常数为8以上的第一高k层。类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。第二高k层具有与第一高k层不同的材料组成。

6. 发明申请

US20050148127A1 Semiconductor device including gate dielectric layer formed of high dielectric alloy and method of fabricating the same 审中-公开
标题翻译：包括由高介电合金形成的栅极介电层的半导体器件及其制造方法
公开(公告)号：US20050148127A1
公开(公告)日：2005-07-07
申请号：US10989200
申请日：2004-11-15
申请人： Hyung-Suk Jung , Jong-Ho Lee , Seok-Joo Doh , Yun-Seok Kim
发明人： Hyung-Suk Jung , Jong-Ho Lee , Seok-Joo Doh , Yun-Seok Kim
IPC分类号： H01L21/336 , H01L21/28 , H01L29/51
CPC分类号： H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device is disclosed comprising an improved gate dielectric layer formed of a high dielectric alloy-like composite together with a method for fabricating the same. The semiconductor device comprises a semiconductor substrate and a gate dielectric layer consisting essentially of a high-k alloy-like composite containing a first element, a second element, and oxygen (O). The first element is at least one member selected from a first group consisting of Al, La, Y, Ga, and In. The second element is at least one member selected from a second group consisting of Hf, Zr, and Ti. A diffusion barrier is formed on the gate dielectric layer, and a gate is formed on the diffusion barrier.
摘要翻译：公开了一种半导体器件，其包括由高介电合金样复合材料形成的改进的栅介质层及其制造方法。半导体器件包括半导体衬底和基本上由含有第一元素，第二元素和氧（O）的高k合金样复合材料组成的栅极电介质层。第一元素是选自由Al，La，Y，Ga和In组成的第一组中的至少一种。第二元素是选自由Hf，Zr和Ti构成的第二组中的至少一种。在栅介电层上形成扩散阻挡层，在扩散阻挡层上形成栅极。

7. 发明授权

US07037863B2 Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices 有权
公开(公告)号：US07037863B2
公开(公告)日：2006-05-02
申请号：US10659945
申请日：2003-09-10
申请人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02323 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3143 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

8. 发明申请

US20060257563A1 Method of fabricating silicon-doped metal oxide layer using atomic layer deposition technique 审中-公开
标题翻译：使用原子层沉积技术制造掺杂硅的金属氧化物层的方法
公开(公告)号：US20060257563A1
公开(公告)日：2006-11-16
申请号：US11329696
申请日：2006-01-11
申请人： Seok-Joo Doh , Shi-Woo Rhee , Jong-Pyo Kim , Jung-Hyoung Lee , Jong-Ho Lee , Yun-Seok Kim
发明人： Seok-Joo Doh , Shi-Woo Rhee , Jong-Pyo Kim , Jung-Hyoung Lee , Jong-Ho Lee , Yun-Seok Kim
IPC分类号： C23C16/00
CPC分类号： C23C16/401 , C23C16/45529 , C23C16/45531
摘要： There are provided methods of fabricating a silicon-doped metal oxide layer on a semiconductor substrate using an atomic layer deposition technique. The methods include an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon-doped metal oxide layer formation cycle Q times. At least one of the values K and Q is an integer of 2 or more. K and Q are integers ranging from 1 to about 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, and then injecting an oxide gas into the reactor. The silicon-doped metal oxide layer formation cycle includes supplying a metal source gas including silicon into a reactor containing the substrate, and then injecting an oxide gas into the reactor. The sequence of operations of repeatedly performing the metal oxide layer formation cycle K times, followed by repeatedly performing the silicon-doped metal oxide layer formation cycle Q times, is performed one or more times until a silicon-doped metal oxide layer with a desired thickness is formed on the substrate. In addition, a method of fabricating a silicon-doped hafnium oxide (Si-doped HfO2) layer according to a similar invention method is also provided.
摘要翻译：提供了使用原子层沉积技术在半导体衬底上制造掺硅金属氧化物层的方法。这些方法包括重复进行金属氧化物层形成循环K次的操作和重复进行掺硅金属氧化物层形成循环Q次的操作。值K和Q中的至少一个是2以上的整数。 K和Q分别为1至约10的整数。金属氧化物层形成循环包括将金属源气体供给到包含基板的反应器中，然后将氧化物气体注入到反应器中的步骤。掺杂硅的金属氧化物层形成循环包括将含有硅的金属源气体供给到含有该基板的反应器中，然后将氧化物气体注入反应器。重复执行金属氧化物层形成循环K次的操作顺序，随后重复进行掺杂硅的金属氧化物层形成循环Q次，执行一次或多次，直到具有所需厚度的掺硅金属氧化物层形成在基板上。此外，还提供了根据类似的发明方法制造掺杂硅的氧化铪（Si掺杂的HfO 2 N 2）层的方法。

9. 发明申请

US20060022252A1 Nonvolatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20060022252A1
公开(公告)日：2006-02-02
申请号：US11193231
申请日：2005-07-29
申请人： Seok-Joo Doh , Jong-Pyo Kim , Jong-Ho Lee , Ki-Chul Kim
发明人： Seok-Joo Doh , Jong-Pyo Kim , Jong-Ho Lee , Ki-Chul Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/513 , H01L29/792
摘要： There are provided a nonvolatile memory device and a method of fabricating the same. A gate region of the nonvolatile memory device is formed as a stack structure including a tunnel oxide layer, a trapping layer, a blocking layer and a control gate electrode. The trapping layer is formed of a high-k dielectric having a higher dielectric constant than that of the tunnel oxide layer. When the trapping layer is formed of high-k dielectric, an EOT in a same thickness can be reduced, and excitation of electrons of the control gate electrode to the tunnel oxide layer due to a high potential barrier relative to the tunnel oxide layer is prevented so that program and erase voltages can be further reduced. As such, a problem that the tunnel oxide layer is damaged due to the conventional high program and erase voltages can be solved by reducing the program and erase voltages, and program and erase speeds of the transistor can be further improved.
摘要翻译：提供了一种非易失性存储器件及其制造方法。非易失性存储器件的栅极区域形成为包括隧道氧化物层，俘获层，阻挡层和控制栅电极的堆叠结构。捕获层由具有比隧道氧化物层的介电常数更高的介电常数的高k电介质形成。当捕获层由高k电介质形成时，可以减小相同厚度的EOT，并且防止由于相对于隧道氧化物层的高势垒而使控制栅电极的电子激发到隧道氧化物层从而可以进一步减少编程和擦除电压。因此，通过减少编程和擦除电压可以解决隧道氧化物层由于常规的高编程和擦除电压而损坏的问题，并且可以进一步提高晶体管的编程和擦除速度。

10. 发明申请

US20050037630A1 Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices 有权
标题翻译：在集成电路器件中在界面层上形成高介电层的后热处理方法
公开(公告)号：US20050037630A1
公开(公告)日：2005-02-17
申请号：US10659945
申请日：2003-09-10
申请人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02323 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3143 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
摘要翻译：可以将通过氧化，退火，氧化，氧化，氧化，氧化，氧化钇和/或其他金属氧化物和/或硅衬底上的其它金属氧化物和硅酸盐形成的高介电层氮化和后热处理，或氧化和退火的组合以形成具有优异迁移率和界面特性的高介电层。

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